Sidense 1T-OTP Memory Macros meet JEDEC Accelerated Testing Qualifications at Two TSMC 28nm Process Nodes

SHF Memory IP targets advanced process node designs

Ottawa, Canada – December 26, 2013 – Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that its SHF Non-Volatile Memory (NVM) macros have met stringent JEDEC accelerated testing requirements for TSMC's 28HPM and 28HPL process nodes.

The 28nm HPM node addresses applications requiring high speed as well as low-leakage power and is suitable for many applications from networking and tablets to mobile consumer products. The 28nm HPL low-power node is best suited for cellular baseband, application processor, wireless connectivity, and programmable logic applications.

To meet JEDEC standard reliability test requirements, three lots of SHF devices at each process node underwent 1000 hours of high temperature storage (HTS) and high temperature operating life (HTOL) stress testing with no bit-cell failures. For both process nodes, macro functionality and performance was verified across each of the FF, FS, SF, SS, and TT process corners at read and program temperatures of -40°C to +125°C. All macro configurations were successfully programmed and read in single-ended, redundant and double-redundant read modes.

"Our patented 1T-Fuse™bit-cell architecture allows us to migrate Sidense 1T-OTP macros to shrinking process nodes as they become available," said Rhéal Gervais, Sidense VP of Operations. "We perform rigorous characterization and qualification of our macros at each node and process variant, including JEDEC accelerated testing, to assure our customers that they are getting low-power non-volatile memory that is highly reliable."

About SHF

The Sidense SHF One-Time-Programmable (OTP) memory subsystem is based on a patented 1T-Fuse™ (anti-fuse) bit-cell. The 1T-Fuse bit-cell uses gate oxide breakdown as a robust, non-reversible programming mechanism. Optimized for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.

Sidense SHF memory IP is provided as a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded SoC applications. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self-Test (BIST) RTL. SHF applications include: code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration. 

About Sidense Corp.

Sidense Corp. provides very dense, highly reliable and secure non-volatile one-time programmable (OTP) Logic Non-Volatile Memory (LNVM) IP for use in standard-logic CMOS processes. The Company, with over 115 patents granted or pending, licenses OTP memory IP based on its innovative one-transistor 1T-Fuse™ bit cell, which does not require extra masks or process steps to manufacture. Sidense 1T-OTP macros provide a better field-programmable, reliable and cost-effective solution than flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming and device configuration uses.

Over 110 companies, including many of the top fabless semiconductor manufacturers and IDMs, have adopted Sidense 1T-OTP as their NVM solution for more than 350 designs. Customers are realizing outstanding savings in solution cost and power consumption along with better security and reliability for applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics. The IP is offered at and supported by all top-tier semiconductor foundries and selected IDMs. Sidense is headquartered in Ottawa, Canada with sales offices worldwide. For more information, please visit  www.sidense.com


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