Dolphin Integration launches new AHB compliant Cache controller to meet growing demand for both energy efficient and faster SoC with NVM

Grenoble, France. December 16, 2013 ---- With the goal of improving drastically the PPA mix (Power x Performance x Area) of Non Volatile Memories (NVM) like eFlash or EEPROM, Dolphin Integration announces today R-Stratus-LP, new generation of cache controller.

R-Stratus-LP provides advanced NVM based devices architecture with outstanding gains:

  • Power consumption of embedded or external NVM may be divided by 3X
  • Apparent frequency is accelerated by 3X

R-Stratus-LP is indeed the first L1 Cache Controller with an architecture optimized for Low-Power

  • Architecture designed to minimize the number of accesses to TAG and cache RAM and NVM memory
  • cache line size and associativity both runtime programmable on the fly

This cache controller has also been designed for facilitating its use by SoC integrators

  • Support of AHB-Lite interfaces to ensure easy integration within any MCU subsystem without need for any bridge
  • Separation of TAG and cache RAM memories from R-Stratus logic in order to ease portability across a wide range of process technologies.

For more information about this offering, have a look at the  presentation sheet

Our Application Engineer may help you appreciate fast the expectable improvements thanks to R-Stratus-LP cache controller based on your current NVM specification. Just  click here or contact  Email Contact for more information.




Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Simon Davidmann: A re-energized Imperas Tutorial at DAC
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
DVCon India 2017, Sept 14 - 15, 2017 at The Leela Palace Bengalore India - Sep 14 - 15, 2017
SMTA International 2017 at Rosemont IL - Sep 17 - 21, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy