Tabula Announces Availability of Stylus Compiler Version 2.8.1

Software release features a series of high-performance soft IP and reference designs

SANTA CLARA, Calif., December 9, 2013 –Tabula, Inc., announced today the availability of version 2.8.1 of its Stylus® compiler, supporting its ABAX®2 P-Series of devices. Stylus 2.8.1 includes MoSys’ GigaChip Interface (GCI) and Tamba Networks’ soft IP cores, as well as a high-performance search engine reference design developed in collaboration with Algo-Logic Systems. These and the many other capabilities included in this release are designed to facilitate next-generation 100G networking equipment development and to further improve user experience. 

The new capabilities and design kits introduced in the Stylus 2.8.1 release include:

  • MoSys’ GCI soft IP core: Designed to interface with MoSys’ Bandwidth Engine devices, the 90%-efficient GigaChip interface protocol enables high-bandwidth, high-efficiency chip-to-chip communications necessary for high-performance switching, routing, monitoring, and content processing functions. In addition, the core includes an automatic error recovery mechanism in the event of a channel CRC error to guarantee end-to-end data integrity and system reliability.
  • Tamba Networks’ universal Interlaken soft IP core: Tamba Networks offers the industry’s lowest latency and smallest sized solution for the Interlaken communication protocol. The Interlaken IP core is also highly configurable to match system requirements including bandwidth of up to 600 Gbps and a lane count of up to 32. The initial configurations supported in this release are 12 × 10G and 8 × 7.5G Interlaken and Interlaken Look-Aside. The core is fully compliant to the Interlaken Protocol Definition revision 1.2.
  • Titan IC regular expression processor (RxP) soft IP core: The RxP regular expression processor core is scalable for 10-40 Gb/s throughput.  The core supports a large rule database of up to 10,000 rules using ABAX2P1 on-chip caches or 1M rules using optional, external DDR3 memory. It achieves this combination of high throughput and database depth by handling multiple characters and multiple regular expressions in parallel, including cross packet inspection.  The core operates in an in-line or look-aside, accelerator role.
  • NetASAP search reference design: Created in collaboration with Algo-Logic Systems, the NetASAP reference design provides L2/L3 routing capability for four 10 Gbps Ethernet ports.  Routing logic is implemented using the Algo-Logic ATSE engine with 4K entries and 320-bit keys.  This reference design supports two levels of priority queuing per Ethernet port with configurable queue depth of up to 1MB per port using on-chip memory only. 
  • Northwest Logic’s configurable PCIe Gen 2 soft IP core
  • Up to 15% runtime reduction
  • Added capabilities:  In excess of 200 new features and improvements to usability, including enhanced timing debug capabilities, that contribute to Tabula’s objective to make high-performance design easy.

More about Stylus compiler 

Stylus compiler provides a synthesis, placement, and routing flow familiar to FPGA designers, using industry-standard RTL inputs and design constraints. The suite automatically exploits the unique advantages of Tabula’s 3D Spacetime architecture; unleashing the ABAX2 3PLDs’ unmatched capabilities and achieving unparalleled performance with surprising ease. The software integrates cutting-edge timing-closure technologies, including sequential timing, router-aware placement, and automatic co-optimization of performance and density.  In addition, to help users take full advantage of the ABAX2P1 device’s unmatched embedded RAM capacity and throughput, Stylus compiler transparently infers multi-port memories (up to 24 ports) from RTL, automatically packing small user memories and folding wide user memories into the device’s on-chip RAM blocks.  


Stylus version 2.8.1 is available today.

About Tabula:

Tabula is the industry’s most innovative programmable logic solutions provider, delivering breakthrough capabilities for today’s most challenging systems applications. The company's ABAX2 family of general-purpose 3D programmable logic devices (3PLDs) based on Tabula’s patented Spacetime architecture and supported by its Stylus compiler, sets a new benchmark for the capability of programmable devices at volume price points, enabling re-programmability not only in FPGA applications, but also in those historically served only by ASICs or ASSPs. Headquartered in Santa Clara, California, Tabula has over 130 employees, and has assembled a leadership team consisting of industry veterans and successful entrepreneurs. Tabula is backed by top-tier investors with a long-term view toward enduring market leadership. For more information, please visit the Tabula website at


Sabrina Joseph,
Managing Partner

560 S. Winchester Blvd.,
Suite 500 

San Jose,
CA 95128 

Tel: (408)236-7373 
Email Contact

Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Design Verification Engineer for intersil at Morrisville, North Carolina
Applications Engineer for intersil at Palm Bay, Florida
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise