Cadence Expands Physically Aware Synthesis in RTL Compiler, Improving Power, Performance and Area for Complex Chips

SAN JOSE, CA -- (Marketwired) -- Nov 20, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS)

Highlights:

  • New capabilities in RTL Compiler bring physical considerations earlier in the synthesis process for better quality of results
  • Delivers up to 15 percent improvement in power, performance and area in new version of RTL Compiler

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design automation, today introduced the Encounter® RTL Compiler version 13.1, which includes a new suite of physically aware RTL synthesis capabilities that deliver up to 15 percent improvement in power, performance and area on today's most complex advanced node chip designs that face timing or congestion challenges. These new capabilities are part of a production-ready physical synthesis engine that enables engineers to use physical aware techniques at the earliest phases of synthesis for better silicon results.

"While collaborating with Cadence on the development of several production designs, Fujitsu deployed RTL Compiler's next-generation physically aware RTL synthesis technologies on a 1GHz, eight-CPU core design," said Satoru Yamaguchi, president and chief executive officer of Fujitsu Semiconductor America. "We were able to improve timing and area by more than 10 percent, allowing us to shrink the chips for our customer while demonstrating the benefit of this new synthesis solution."

As geometries shrink beyond 28nm, changes in interconnect characteristics make it much more difficult to achieve optimal timing and closure. The new RTL Compiler capabilities let design teams address these challenges earlier in the design process so they can achieve faster timing closure, while improving performance, power and area.

The new RTL synthesis capabilities include physically aware structuring, mapping, multi-bit cell inferencing and design for test that offer significant benefits for Cadence customers. Physically aware structuring and mapping can improve performance by more than 10 percent and area by more than 15 percent on complex SoCs by considering pin and register placement when deciding which micro-architectures to synthesize to, and how to balance them. Physically aware multi-bit cell inferencing can lower power by more than 10 percent by merging single registers into multi-bit registers that share a clock.

"Cadence has re-architected RTL Compiler to weave physical awareness into stages of RTL synthesis that were traditionally logic only, allowing engineers to leverage floorplan and placement data as early as possible in the flow to ensure correlation with the Encounter Digital Implementation System," said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "Our investment continues in this area, with our customers citing benefits for timing, power, and area in a wide range of target applications and better out-of-box results reducing iterations."

A more detailed description of the new RTL Compiler capabilities can be found at www.cadence.com/news/RTL.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available here.

© 2013 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Cadence Newsroom
408-944-7039

newsroom@cadence.com 





Review Article Be the first to review this article
CST Webinar Series

EMA:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Retail Therapy: Jump starting Black Friday
Peggy AycinenaIP Showcase
by Peggy Aycinena
REUSE 2016: Addressing the Four Freedoms
More Editorial  
Jobs
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
AE-APPS SUPPORT/TMM for EDA Careers at San Jose-SOCAL-AZ, CA
ACCOUNT MANAGER MUNICH GERMANY EU for EDA Careers at MUNICH, Germany
Principal Circuit Design Engineer for Rambus at Sunnyvale, CA
Manager, Field Applications Engineering for Real Intent at Sunnyvale, CA
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Upcoming Events
Zuken Innovation World 2017, April 24 - 26, 2017, Hilton Head Marriott Resort & Spa in Hilton Head Island, SC at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
CST Webinar Series



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy