Vivado Design Suite 2013.3 Accelerates Productivity with Design Methodology, Next Generation Plug-and-Play IP, and Partial Reconfiguration

Vivado Design Suite 2013.3 extends design flows and revolutionizes IP ease of use

SAN JOSE, Calif., Oct. 23, 2013 — (PRNewswire) —  Xilinx, Inc. (NASDAQ: XLNX) today released the Vivado Design Suite 2013.3, featuring support for the new UltraFast design methodology, enhanced configuration, integration and verification of Plug-and-Play IP, and Partial Reconfiguration. The Vivado® Design Suite is co-optimized with Xilinx's All Programmable devices and is the programmable industry's only SoC-strength design suite able to address the productivity bottlenecks in system-level integration and implementation.

Automated Support for the New UltraFast Design Methodology
To enable accelerated and predictable design cycles, Vivado Design Suite 2013.3 provides built-in automation of critical aspects of the UltraFast design methodology, providing design rule checks (DRC) guiding engineers throughout the design cycle and HDL and constraints templates enabling optimal quality of results.

Enhanced Configuration, Integration, and Verification of Plug-and-Play IP
Xilinx's Plug-and-Play IP initiative, introduced in 2012, leverages industry standards such as IP-XACT, IEEE P1735 encryption and the AMBA® AXI4 interconnect protocol to accelerate integration of IP. Earlier this year, the Vivado Design Suite shattered the RTL design productivity plateau by providing the industry's first plug-and-play IP integration design environment with its IP Integrator capability.

The Vivado Design Suite 2013.3 release adds a major ease-of-use improvement with enhanced IP integration and offers over 230 LogiCORE™ and SmartCORE™ IP cores. This release upgrade allows for system-wide co-optimization of a design and Xilinx IP. For instance, designers can now share clocking resources throughout their design with connectivity IP such as Ethernet MAC or PCIe®. Upgrades to the IP also provide easy top-level access to transceiver debug ports within the IP. With new capabilities to the Vivado logic analyzer, designers have full read-and-write access to their AXI system, at runtime. They can also perform hardware debug using advanced trigger feature to detect and capture complex events.

This release also further eases the IP integration with revision control systems and automates the verification flows with the Cadence Incisive Enterprise simulator and the Synopsys VCS simulator.

Partial Reconfiguration
The Vivado Design Suite 2013.3 introduces support for Partial Reconfiguration, which has been successfully used by many customers with the ISE Design Suite. This technology enables greater usage of device resources by dynamically swapping functions on demand. Partial Reconfiguration can also result in lower power consumption and can enable field updates with no system downtime.

"Utilizing Xilinx's Partial Reconfiguration feature in Vivado for 7 series devices has empowered Trendium to achieve a successful system on chip architecture while simultaneously meeting our PCI Express® requirements," said Stephen Frey, Firmware Engineering Manager at Trendium, Inc.  "Partial Reconfiguration has allowed us to more efficiently utilize Xilinx silicon by interchanging protocol analysis modules for our Network Access Agent platform without disrupting the PCI Express link.  This approach also provides a path to upgrade the existing hardware with new modules for future product enhancements."

Download the Vivado Design Suite 2013.3 today at Sign up for or view online training for Vivado Design Suite, and take advantage of the UltraFast design methodology and the Vivado Design Suite-based Targeted Reference Designs to jumpstart your productivity.

About Xilinx
Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit



© Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA is a registered trademark of ARM in the EU and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license.  All other trademarks are the property of their respective owners.

Silvia E. Gianelli
(408) 626-4328
Email Contact

SOURCE Xilinx, Inc.

Xilinx, Inc.

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy