Dolphin Integration offers first standard cell library to enable a leakage reduction of 1/350 at 65 and 55 nm

Grenoble, France - Oct 18, 2013 ---- Dolphin Integration, the innovator of Virtual Components for density and power optimized subsystems, announces the SESAME BIV standard cell library as a major innovation for ultra low leakage always-on logic block.

SESAME BIV standard cell library extends the RCSL offer (Reduced Cell Stem Libraries) by delivering a leakage reduction of 1/350 for a silicon footprint up to  7x denser for a 5,000-gate block implemented with a usual HVT standard cell combined with its dedicated low quiescent linear regulator.

SESAME BIV is ideal for always-on clock islets such as real-time clocks (RTC) as well as RF or voice awakening devices.

SESAME BIV incorporates the key features needed for such always-on logic islets:

  • A patented Flip Flop to reliably sustain operating voltage range from 1.2 V up to 3.3 V, eliminating the need for a voltage regulator
  • A design based on 2.5 V transistors with overdriven thick gates and 10-track cells to get a higher density
  • Data retention guaranteed at very low voltage (e.g. 0.5 V at 65 nm) for ultimate power savings

Decreasing power is a global requirement requiring diverse solutions where SESAME BIV illustrates Dolphin Integration’s commitment to go beyond a standard offering for low leakage. SESAME BIV enables an innovative but safe, energy efficient, and dense implementation of critical logic”, announces Elsa BERNARD-MOULIN, Library Marketing Manager. “We are glad to announce that Customers of major foundries such as TSMC and Global Foundries have already selected this SESAME BIV”.

For more information on the key benefits and performances of SESAME BIV standard cell library, have a quick look on  our catalog.




Review Article Be the first to review this article
CST: Webinar

Aldec Simulator Evaluate Now

Featured Video
Jobs
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
RF IC Design Engineering Manager for Intel at Santa Clara, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise