Video Preview: Real Intent to Present Keynote Address at FMCAD in Portland, Ore. on Oct. 23

Who

Dr. Pranav Ashar, Chief Technology Officer at Real Intent, whose advanced verification solutions accelerate electronic design sign-off, will present one of two keynote addresses next week at FMCAD – the Formal Methods in Computer-Aided Design conference.

What

Static Verification Based Signoff – A Key Enabler for Managing Verification Complexity in the Modern SoC.” The 1½-hour presentation focuses on application-based verification, in which the verification process is partitioned by verification concerns. This important approach and new paradigm for managing verification complexity in billion-transistor SoCs – whose layers of complexity extend beyond the baseline complexity of their constituent components – makes the analysis and debug dimensions of the verification problem meaningfully solvable. It narrows the verification scope to issues such as clock-domain verification, power, and DFT, in which static formal analysis plays a key role. The presentation emphasizes the development of complete solutions and closure for the problem at hand as a whole, rather than just nuts-and-bolts technology such as simulation and ABV. For example, with hundreds of clock domains on a chip now, dedicated sign-off of clock-domain crossings requires verification tools specialized for this purpose. SoC tape-out no longer can be completed solely by functional simulation or static timing analysis; instead it requires a solution with formal verification at its core. The keynote presentation explores numerous reasons why static formal analysis plays a major role in the new application-based verification paradigm.

Dr. Ashar, with two decades of experience in EDA, previously spent 13 years at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He has authored approximately 70 papers with more than 1,000 citations, and co-authored a book, Sequential Logic Synthesis. He has 35 patents granted and pending, and has taught graduate and undergraduate courses on VLSI design automation, VLSI verification, and VLSI design as an adjunct faculty member at Columbia University. He holds a Ph.D. in EECS from UC Berkeley.

When/Where

Conference:  Monday, Oct. 21 – Wednesday, Oct. 23, 2013
Keynote:  Wednesday, Oct. 23, 2013, 9 -10:30 a.m., Columbia Falls Ballroom (2nd floor)
University Place Hotel & Conference Center
310 SW Lincoln St.
Portland, Ore. 97201
+1.866.845.4647

About FMCAD

FMCAD 2013 is the 13th in a series of conferences on the theory and application of formal methods in hardware and system design and verification.  FMCAD provides a leading international forum to researchers and practitioners in academia and industry for presenting and discussing groundbreaking methods, technologies, theoretical results, and tools for reasoning formally about computing systems. FMCAD covers formal aspects of computer-aided system design including verification, specification, synthesis, and testing. Real Intent is one of more than a dozen sponsors of this conference.

About Real Intent

Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.

Acronyms
ABV: Assertion-Based Verification
CDC: Clock Domain Crossing
DFT: Design For Test
EDA: Electronic Design Automation
EECS: Electrical Engineering & Computer Science
RTL: Register Transfer Level
SoC: System-on-Chip

Meridian and Ascent are trademarks of Real Intent, Inc. All other trademarks and trade names are the property of their respective owners.

Press contact:
Sarah Miller for Real Intent
ThinkBold Corporate Communications
231.264.8636
Email Contact




Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Blue Pearl: Best kept Secret in EDA
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise