Media Alert: White Paper Details Speed-Power Benefits of DDC Transistor Technology Validated in ARM Processors and Memory Circuits

LOS GATOS, CA -- (Marketwired) -- Sep 26, 2013 --


What:
Controlling power consumption is the greatest challenge for chip designers. In the white paper entitled: "SuVolta's DDC Technology: A Complementary Technology to ARM Embedded Processors for Power Optimized Application," SuVolta describes significant power reduction results and operating speed (performance) enhancements demonstrated in a system-on-a-chip (SoC) test chip incorporating ARM Cortex-M0 processors and static random-access memory (SRAM). Elements of the white paper were published in a paper in the proceedings of the IEEE Custom Integrated Circuits Conference (CICC), held in San Jose, California, September 23 - 25, 2013.

Why:
The process technology used by the semiconductor industry for the past 40 years -- conventional bulk planar CMOS -- is hitting active and leakage power limits, and voltage scaling has stagnated at ~1 Volt for the past 10 years. Power dissipation has become the primary architectural limiter for mobile SoCs. The total power consumption in a SoC constrains both the thermal envelope and the battery life of mobile products.

One major implication of this barrier is manifested in the semiconductor industry's constant struggle to reduce power consumption and increase battery life of mobile devices without sacrificing performance or cost.

Deeply Depleted Channel™ (DDC) technology and DDC-optimized circuits and design techniques enable scaling (reduction) of two of the most critical transistor parameters -- scaling of supply voltage, and scaling of transistor size to the sub-20nm node. DDC technology applies across a wide range of integrated circuit (IC) products, including processors, memories, and SoCs that are critical to today's mobile products.

Who:
SuVolta, Inc.

Where:
The white paper can be access on SuVolta's web site at: http://www.suvolta.com/files/2513/7996/4535/SV_NK_P_130920_ARM_SuVolta_Whitepaper_Final.pdf.

When:
The white paper is available as of September 26, 2013.

Contacts:
Margo Westfall
SuVolta, Inc.
+1 (408) 429 6058

Email Contact

Steve Jursa
The Hoffman Agency 
+1 (408) 975 3029

Email Contact 





Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
Verific: SystemVerilog & VHDL Parsers



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy