Preview for ITC for JTAG Technologies for ITC 2013, Disneyland Hotel, Anaheim, September 10-12, Booth # 218

Eindhoven , August 2013 –JTAG Technologies BV (Eindhoven, The Netherlands), a vendor of test and debug tools based on boundary-scan, will showcase the following JTAGLive products as well as new systems upgrades at this years’ ITC show in Anaheim.

JTAGLive CoreCommander – Quick and Easy to Learn and to Use

Engineers can now activate the OCD (On-Chip Debug) modes of a range of popular cores to affect ‘kernel-centric’ testing. While many devices are now equipped with JTAG (IEEE Std. 1149.1) boundary-scan registers (BSRs), which are used extensively to provide test access into digital and mixed-signal designs, a significant number of microprocessors and DSPs can be found with deficient or even non-existent boundary-scan test registers. For the electronics test engineer this can, at best, be ‘frustrating’ as they look to employ alternative methods for testing the ’processor and/or associated cluster/peripheral components.

CoreCommander routines are ideal for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair, since no on-board code is required to set memory reads and writes. Boundary-scan deficient parts can also be better utilised during production test, as CoreCommander-driven functions increase fault coverage. Since CoreCommander is Python-based it complements perfectly the JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronised testing to full boundary-scan devices.

The solutions take control of key processor core functions using the built-in emulation/debug functions of the ‘processor core and are designed by test engineers for use by test engineers. JTAG CoreCommander uses dual modes of operation, namely ‘Interactive’ or ‘Python embedded’.

More Features – the new JTAG CoreCommander checks-out the FPGA Zone

CoreCommander for FPGAs is a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port (TAP) to proprietary IP cores (e.g. DDR controllers, E-net MAC, USB controllers etc..) and harness them for test purposes.

The base of CoreCommander for FPGAs is a RTL (Register Transfer Language) coded translator block that provides access to proprietary IP cores through commonly implemented bus structures such as ‘Wishbone’, AMBA, Avalon and CoreConnect. This translator block can either be permanently or temporarily programmed into a gate–array. Linker software provided with the module automatically links the translator block with IP blocks and the FPGA specific interface layer to build the complete file set that may be programmed in the FPGA. Access to the translator is subsequently provided by a Python (JFT) library module.

JTAG Live Studio

This is our latest comprehensive package of JTAG/boundary-scan tools that enable designers and manufacturing test engineers alike to develop complete test and programming applications.


The benefits offered by the JTAG Technology for debugging, testing and in-system programming are not limited to complex designs with many JTAG devices. Designs with only a few, even just one or two, JTAG devices can also greatly benefit from this technology during all stages of the life cycle. A toolset capable of handling even the most (very) complex boundary-scan designs, however, often is not economically feasible for a company that only uses a few JTAG devices in its designs.



JTAG Live Studio establishes a new class of test and device-programming tool-set that dramatically lowers the cost of entry for test- and hardware engineers.  Alongside the many traditional benefits of JTAG/boundary-scan JTAG Live Studio gives access to newer technologies like processor-controlled test.

Python-embedded mode uses a similar structure to that featured in the JTAGLive Script product, allowing CoreCommander functions to be embedded into Python code to create re-usable test modules for specific tests.

About JTAG Live

JTAG Live is the economic easy-to-use family of board debug tool from JTAG Technologies. Products within the family include Buzz, AutoBuzz, Clip and Script. For more information please visit www.jtaglive.com

About JTAG Technologies

JTAG Technologies is a market leader and technology innovator of boundary-scan software and hardware products and services. The company was the first to bring to the market such important advances as automated test generation, automated fault coverage analysis, automated flash and PLD programming via boundary-scan, and visualized boundary-scan analysis. Its customers include world leaders in electronics design and manufacturing such as Ericsson, Flextronics, Honeywell, Medtronic, Motorola, Nokia, Philips, Raytheon, Rockwell-Collins, Samsung, and Sony. Its innovative boundary-scan products provide test preparation, test execution, test result analysis and in-system programming applications. With an installed base of over 6500 systems worldwide, JTAG Technologies serves the communications, medical electronics, avionics, defence, automotive, and consumer industries with offices throughout North America, Europe and Asia. JTAG Technologies headquarters are located in Eindhoven, The Netherlands. For more information please visit www.jtag.com


Contact: 

Renate Fritz,
email: Email Contact  




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy