Aldec Webinar: Accelerate SoC Simulation Time of Newer Generation FPGAs

Presenter:          Bill Tomas - Aldec Research Engineer  

Date: Thursday, August 8, 2013

Time: 11:00 AM - 12:00 PM PDT Register for US Session

Time: 3:00pm - 4:00pm CEST Register for European Session


Functional verification of a design at the three design stages (RTL, Gate-Level and Post-Route) are essential steps to ensure correct behavior of a design according to requirements, however they are limited by HDL simulator speed. While HDL simulators offer advanced debugging capabilities and provide robust design coverage information, their speed is the primary bottleneck of the design cycle when it comes to verification.  This webinar will discuss a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. 


  • Function Verification Challenges
  • HES HW/SW Emulation Overview
  • HES-7 SoC / ASIC Prototyping Board
  • Problem Solving Scenarios
  • What is Simulation Acceleration?
  • Improving Simulation Speed
  • Advanced Debugging
  • Demo and Q & A

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