Timevision-CDC checks that asynchronous clock domain crossings are safe
AUSTIN, Texas — (BUSINESS WIRE) — June 3, 2013 — Ausdia, the leading developer of timing constraints verification and management solutions that complement timing signoff for complex system-on-chip (SoC) designs, introduced an add-on product for its comprehensive Timevision timing constraints development, verification and management solution at DAC 2013. Timevision-CDC checks the safety of asynchronous clock domain crossings while simultaneously leveraging and verifying the SDC (Synopsys design constraint) file that specifies the asynchronous relationships.
SoC designs in custom silicon are getting progressively more complicated and harder to design and verify, as well as consuming greater quantities of IP. Designers are creating SoC designs with hundreds to thousands of clocks, but find that they are unable to sign off clock domain crossing verification at the chip level, or even the major partition level, without resorting to complex hierarchical methodologies and extensive rework to generate the appropriate CDC constraints. As the only tool that is 100% driven from SDC and that directly uses the asynchronous relationships specified, Timevision-CDC advances the state of the art. It is the first to perform true multimode CDC with zero designer input. Designers are able use the tool to achieve 100% correlation between RTL- and gate-level designs. The performance of the tool allows for tasks that take tens of hours in other tools to be accomplished 10-30 minutes in Timevision.
“We listened to our customers’ extensive frustrations and requirements for a next-generation CDC signoff solution,” said Sam Appleton, CEO of Ausdia. “The result is a product that is 100% integrated with the SDC verification environment, allowing for even greater coverage of the timing verification specifications. Since Timevision-CDC has the same massive capacity and performance advantages as Timevision, the need to create complex hierarchical verification flows is eliminated.”
- is the only tool that offers multi-clock and multi-mode CDC, ensuring that designers don’t have to define and wade through a hundred different modal CDC runs that have no correlation to timing signoff.
- is able to run fully flat or with "greybox" or "whitebox" treatment of IP and hierarchies. All users to date have been working with large amounts of IP reuse; Timevision-CDC is the only tool that can easily verify only the interfaces of the IP.
- allows designers to start using the tool with almost zero setup, since it is SDC-based and most partition or full chip designs have only SDC constraints.
- allows designers to do CDC signoff in the timing signoff environment, since SDC constraints are used for tapeout.
- provides a fully-integrated SDC and CDC solution, making it the only tool in the industry that can verify the clock groups created by the designers.
- offers unparalleled performance and capacity: for example, verifying a120M-gate SoC in 3 hours, 2B gates in less than 12 hours. It is the first product in the industry that has a proven capacity above the 1 Billion gate mark, running flat.
Timevision-CDC is a fully integrated add-on to Ausdia’s Timevision product. As a timing constraints generation and validation product, it is designed to match static timing analysis engines, using threading to achieve performance. A formal verification engine with innovative techniques allows for timing exception verification. A patented feature called “automated clock grouping” enables multimode CDC without generating massive quantities of noise. This technology is both new to the industry and a new technology application for the CDC market.
Pricing and Availability
Timevision-CDC is available now. U.S. pricing for a yearly add-on to Timevision is $60k per license.
Ausdia is exhibiting Timevision and Timevision-CDC in Booth # 633 at DAC 2013 in Austin, Texas, from June 3rd to June 5th.
Timevision is a comprehensive timing constraints development, verification and management solution that complements all implementation and timing signoff flows. Introduced at DAC 2012, Timevision integrates with all aspects of the design flow and is used before synthesis, before DFT insertion, before place and route, and when signoff timing is being run. Timevision helps designers create good SDC/TCL constraints and is a verification platform for existing timing constraints.
delivers standout timing constraint development, verification, and
management solutions that complement all implementation and timing
signoff flows. The company’s groundbreaking methodology and products
give system-on-chip (SoC) and integrated circuit (IC) developers a new
way to work, enabling massive productivity gains throughout the design
flow. Founded in 2006, the privately-held company is headquartered in