Enhancements to physical implementation tools include:TSMC 16nm FinFET support, Statistical OCV, Physical-Aware Scope-based Sign-off timing ECO’s, Virtual-Flat Methodology for Rapid Prototyping
SANTA CLARA, Calif. — (BUSINESS WIRE) — May 30, 2013 — ATopTech, the leader in next generation physical design solutions that address the challenges of designing integrated circuits (ICs), will introduce significant technology additions and performance gains in software release AP 13.02 (release 2.0) for its AprisaTM and ApogeeTM tools at the 50th DAC in Austin, Texas. Aprisa is the company’s complete place and route (P&R) engine, including placement, clock tree synthesis, optimization, global routing, and detailed routing. Apogee is a complete top down floorplanning and chip assembly tool that complements Aprisa.
Highlights of Release 13.02 include:
- Certified TSMC 16nm FinFET v. 0.1 support with color-aware double patterning technology (DPT) routing and FinFET-aware placement, offering improved design performance, lower overall power, and smaller area. This combined with Aprisa’s patented color-aware technology guarantees that there will be no odd cycle violations in DPT designs.
- A comprehensive Statistical On-Chip Variation (SOCV) methodology, proposed by TSMC, for better modeling of the variability challenge at 16nm. This approach dramatically reduces the pessimism associated with traditional OCV methodologies.
- Physical-Aware Scope-based Sign-off (PASSTM) timing ECO, which delivers fast physically-aware ECOs and timing closure based on sign-off timing information and scope-based timing analysis technology. PASS dramatically reduces memory and run time requirements while providing far fewer ECO loops than traditional ECO methods.
- Virtual Flat TM Methodology, which enables fast and accurate timing-driven feed-through insertion and timing budgeting with simultaneous global-path timing optimization. This technique greatly reduces the iterative loops while floorplanning. In addition, In-Hierarchy Optimization (iHO) enables simultaneous optimization across hierarchical boundaries without flattening the design. Top-level design closure becomes much easier with this approach, allowing one designer to close top-level timing without having to involve all the block-level designers. Again, iterative loops are greatly reduced.
“Preparing users for 16nm FinFET design continues ATopTech’s commitment to develop and deliver cutting-edge place-and-route technology that enables our customers to meet the challenges of 20nm and 16nm design,” said Jue-Hsien Chern, CEO of ATopTech.
Release 13.02 of Aprisa and Apogee are available immediately. The technology will be demonstrated in Booth # 2033 at DAC 2013 in the Austin Convention Center, Austin, Texas, from June 3-5. To schedule a private meeting or demonstration, please visit www.atoptech.com.
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. For more information, see www.atoptech.com
Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Cayenne Communication LLC
Michelle Clancy, 252-940-0981