Airics and HDL Design House introduce the Latest Trends in Verification of FPGA & ASIC

When/Where:

June 13th, 2013
9.00 - 12.30

Memory Hotel, konferensrum Kaptenen
Borgarfjordsgatan 3
164 25 Kista

Visit Airics: www.airics.se

Agenda and Speakers' Topics:

9.00 am - 9.15 am Introduction of Airics and HDL Design House
Ulf Orrebrink, Airics General Manager and co-founder

9.15 am - 10.00 am HDL Design House Products and Services Overview
Bogdan Bizic, HDL Desgin House Managing Director

10.00 am - 10.45 am Background, Motivation & Trends in Verification
Olivera Stojanovic, Senior Staff Verification Engineer

10.45 am - 11.00 am Coffee Break

11.00 am - 11.45 am HDL Design House Verification Flow and Experience
Olivera Stojanovic, Senior Staff Verification Engineer

11.45 am - 12.00 pm Q&A

12.00 pm - 12.30 pm Lunch




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