Concept Engineering Adds SPEF Parasitic Netlist Interface to SpiceVision® PRO and StarVision® PRO

New interface accelerates analysis and simulation of post-layout netlists and will be demonstrated at DAC 2013

FREIBURG, Germany — (BUSINESS WIRE) — May 28, 2013Concept Engineering has added a new SPEF (standard parasitic exchange format) interface to their widely-installed debugging tools, SpiceVision® PRO and StarVision® PRO. SpiceVision PRO takes SPICE netlists and SPICE models and generates clean, easy-to-read transistor-level schematics, circuit fragments, and design documentation to speed up circuit design, circuit debugging and circuit optimization at the transistor level. StarVision PRO, an integrated debugging cockpit for Mixed-Signal design, makes analysis and debugging of complex SoC (system on chip) and IC (integrated circuit) designs easy and more transparent.

Shrinking semiconductor process geometries and increased number of metal layers, interconnections and components create an enormous number of parasitic devices during netlist extraction and create a severe situation for simulation and signoff engineers. The new SPEF interface, and the already-available DSPF (Detailed Standard Parasitic Format) interface, give design engineers using SpiceVision PRO and StarVision PRO an easy way to analyze and explore parasitic structures in order to better understand, manage and optimize timing, signal integrity or IR-drop within their designs. The SPEF file format is an IEEE standard to define parasitic networks and contains precise information about interconnections and the related parasitic components.

Concept Engineering’s new SPEF interface provides engineers with very detailed information about the post-layout interconnections on their chips, allowing them to easily visualize and explore parasitic netlists and to precisely locate and understand post-layout problems. In addition the new technology provides a very comfortable way to isolate and generate post-layout SPICE netlists of specific critical circuit fragments. Such isolated netlist fragments can then be used for fast and detailed circuit simulation and result in significantly accelerated post layout simulation.

“Concept Engineering is focused on providing design and verification engineers with the best possible ways to understand and analyze complex design descriptions from different sources, different design languages and on different design levels,” said Gerhard Angst, CEO and president of Concept Engineering. “Now, with two dedicated interfaces available, customers will be able to more easily understand and manage extracted parasitic netlists and the impact of parasitic elements on their designs. The SPEF and DSPF interfaces provide users with a comfortable way to visualize and analyze the most important post-layout data formats of today’s advanced design flows.”

Pricing and Availability

The SPEF interface for StarVision PRO is available at no additional cost. For SpiceVision PRO, the SPEF interface is available as part of the optional “Parasitic Analysis Package.”

Both interfaces will be featured in product demonstrations in booth #1842 at DAC 2013 in Austin, Texas, from June 3-5. Production versions will be available shortly after DAC.

About Concept Engineering

Concept Engineering is a privately held company based in Freiburg, Germany, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, circuit characterization, circuit optimization, test automation and physical design tools. The company's customers are primarily EDA tool manufacturers (OEMs), in-house CAD tool developers and semiconductor companies.

SpiceVision PRO, GateVision PRO, RTLvision PRO and StarVision PRO are registered trademarks and Nlview and T-engine are trademarks of Concept Engineering GmbH. All other trademarks are property of their respective owners.



Contact:

Cayenne Communication LLC for Concept Engineering in North America:
Michelle Clancy, +1-252-940-0981
Email Contact




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise