ANDOVER, Mass. — (BUSINESS WIRE) — May 23, 2013 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of release 2.0 of its patented SimXACT and XOPT X analysis solutions including major new features for analyzing and automatically eliminating X bugs in RTL and gate-level design simulation.
XOPT Sim is a new simulation and heuristic-based X optimism solution which automatically biases the simulated execution paths in RTL to expose a larger state space resulting from non-determinism than what is possible with the Verilog simulation standard. This way the design can be more fully validated in the presence of Xs in conditional assignments. Other solutions inject Xs in registers when Xs are involved in their conditional assignments, however this can prove to be overly pessimistic and lockup the RTL simulation rendering the results useless and force designers to debug the cause of a pessimistic X, only to find out that there is no actual design problem. The complete RTL X Optimism solution combines using XOPT Sim and XOPT Formal, a formal analysis to uncover register-to-register X propagation masked by X optimism including sequential backtracing to the X source.
XTrace is a new sequential X analysis option to SimXACT. Users can now perform focused analysis of sequential X traces by identifying certain registers. XTrace will analyze the sequential backtrace of the X paths to find and correct any X-pessimism found on the path as well as generating a concise backtrace report to review the Xs, either real or resulting from X-pessimism.
Safe Deposit Analysis is a new formal based solution to generating a list to non-resettable registers which can be safely deposited a random value at time zero because they don’t have controlling behavior through the reset sequence. Safe Deposit is precise and accurate because it uses formal methods to determine X controllability on the fanout of nonreset registers. This has been shown to reduce the number of X pessimism cases found by SimXACT.
Other improvements to SimXACT include new plug’n’play setup and supporting distributed analysis that scales to designs of 100Ms gates.
SimXACT and XOPT Formal provide comprehensive solutions to addressing the inherent limitations of handling non-determinism associated with X values in logic simulation rendering simulation results which may not reflect actual hardware operation and cause real X design bugs. Avery X verification uses formal methods to accurately analyze X propagations enabling engineers to:
- Run gate-level simulations free of X pessimism issues
- Diagnose occurrences of X optimism in RTL simulations alerting designers who may be unaware of potential non-deterministic sequential behaviors
- Perform sequential X propagation forward and backward tracing and debug
- Accurately analyze and report X states during hardware reset and power transition sequences to confirm design specs
- Generate list of non-resettable registers for safe deposit at time zero
Visit us at the Design Automation Conference (DAC) June 3-7 in booth #1835 and come see our Designer Track presentation, “5.4 - Automated Method Eliminates X Bugs in RTL and Gates”, on Tuesday, June 4, 2013 from 4:00 PM - 6:00 PM at Location 18C.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for automatic property and coverage generation and RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, NVM Express, SCSI Express, eMMC, and SD/SDIO standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Avery Design Systems
Chris Browy, 978-689-7286