Oasys Announces Floorplan Compiler

Creates Floorplan from RTL in Days that Meets Constraints as Initial Guidance to P&R Teams

SANTA CLARA, Calif. — (BUSINESS WIRE) — May 20, 2013 — Oasys Design Systems announced the immediate availability of Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. Synthesis engineers, architects and RTL designers can now create a floorplan directly from the RTL that is aware of the designs dataflow and also meets timing, power, area and congestion constraints. The resulting floorplan can then be fed forward as initial guidance to physical design teams. Oasys RealTime Floorplan Compiler has been production proven over the last four years, but until now has not been available as a separate tool.

Reduces Time to get Initial Floorplan from 4-6 weeks to a Few Days

The ability of Floorplan Compiler to take into consideration regions, fences, blockages and other physical guidance using the advanced floorplan editing tools enables engineers to take an initially compiled floorplan from Oasys, make changes and then re-compile it with the new constraints to keep getting improved versions multiple times per day. “One of the time consuming tasks of the SoC and ASIC design implementation phase is getting a good quality initial floorplan,” stated Scott Seaton, CEO at Oasys. “Oasys RealTime Floorplan Compiler helps our customers reduce the cycle time for this task from 4-6 weeks down to a few days.”

Optimization at the RTL Level and Placement First Methodology

“The uniqueness of Oasys’ RealTime physical synthesis engine is that it optimizes at the RTL level utilizing a placement first methodology,” stated Paul Van Besouw, CTO at Oasys. “This enables Floorplan Compiler to concurrently optimize RTL partitions for the designs dataflow and automatically place macros, pins and pads to come up with a high quality floorplan for the constraints given.”

Plugs into Existing Design Flows

Oasys RealTime Floorplan Compiler takes in standard synthesis inputs and physical guidance if available to create an optimized floorplan. The output is a standard floorplan DEF file which can either be fed into traditional synthesis tools or place & route tools as an initial floorplan to reduce implementation time.

Oasys RealTime Floorplan Compiler is available immediately as an option in the Oasys RealTime suite of design for implementation (DFI) tools. Click here to learn more. Oasys will be demonstrating Floorplan Compiler at the Design Automation Conference (DAC) from June 3-5 in Austin at booth 1231. Click here to request a private presentation and demo in our suite.

About Oasys Design Systems

Oasys Design Systems is a private electronic design automation (EDA) supplier specializing in design for implementation (DFI) tools to reduce the time it takes to implement SoC & ASIC designs. Oasys corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: Email Contact. For more information, visit: www.oasysdesign.com.

Oasys, Oasys RealTime and Oasys RealTime Floorplan Compiler are trademarks of Oasys Design Systems. All other trademarks are the property of their respective owners.


Oasys Design Systems
Scott Seaton, 408-855-8531
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