19th Asia and South Pacific Design Automation Conference 2014
Jan. 20-23, 2014, SunTec, Singapore
Regular paper submission is due 5 PM JST (UTC+9) July 10, 2013
** The deadline is strict this year; the initial submission **
** site will be closed on the deadline, though modification **
** of the PDFs are allowed until July 17. **
Aims of the Conference:
ASP-DAC 2014 is the nineteenth annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world. The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.
Areas of Interest:
Original papers on, but not limited to, the following areas are invited. Please note that ASP-DAC will work cooperatively with other conferences and symposia in the field to check for double submissions.
 System-Level Modeling and Simulation/Verification:
System-level modeling, specification, language, performance analysis, system-level simulation/verification, hardware-software co-simulation/co-verification, etc.
 System-Level Synthesis and Optimization:
System-on-chip and multi-processor SoC (MPSoC) design methodology, hardware-software partitioning, hardware-software co-design, IP/platform-based design, application-specific instruction-set processor (ASIP) synthesis, low power system design, etc.
 System-Level Memory/Communication Design and Networks on Chip:
Memory/cache optimization, Communication-based architecture design, network-on-chip (NoC) design methodologies and CAD, interface synthesis, system communication architecture, memory architecture, low power communication design, etc.
 Embedded and Real-Time Systems:
Embedded system design, real-time system design, OS, middleware. Compilation techniques, memory/cache optimization, interfacing and software issues, with focuses on integration or real-time properties to embedded systems. (Papers for general optimizations in compilers and memory/cache/flash management schemes may be moved to the more suitable subcommittees.)
 High-Level/Behavioral/Logic Synthesis and Optimization:
High-Level/behavioral/RTL synthesis, technology-independent optimization, technology mapping, interaction between logic design and layout, sequential and asynchronous logic synthesis, resource scheduling, allocation, and synthesis.
 Validation and Verification for Behavioral/Logic Design:
Logic simulation, symbolic simulation, formal verification, equivalence checking, transaction-level/RTL and gate-level modeling and validation, assertion-based verification, coverage-analysis, constrained-random testbench generation.
 Physical Design:
a. Partitioning, floorplanning, placement, buffer insertion, interconnect planning, post-placement optimization, cell library design, gate sizing, high-level physical design and synthesis.
b. Routing, clock network synthesis, post-routing optimization, layout verification, package/PCB routing.
 Timing, Power, Thermal Analysis and Optimization:
Deterministic and statistical static timing analysis, statistical performance analysis and optimization, low power design, power and leakage analysis, power/ground and package analysis and optimization, thermal analysis, etc.
 Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation:
Signal/power integrity, clock and bus analysis, interconnect and substrate modeling/extraction, package modeling, device modeling/simulation, circuit simulation, high-frequency and electromagnetic simulation of circuits, etc.
 Design for Manufacturability/Yield and Statistical Design:
DFM, DFY, CAD support for OPC and RET, variability analysis, yield analysis and optimization, reliability analysis, design for resilience and robustness, cell library design, design fabrics, etc.
 Test and Design for Testability:
Testable design, fault modeling, ATPG, BIST and DFT, memory test and repair, core and system test, delay test, analog and mixed signal test.
 Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, analog layout, verification and simulation techniques, noise analysis, mixed-signal design considerations.
 Emerging Technologies and Applications
a. EDA and Design Methodologies for Emerging Technologies:
Nanotechnology, quantum devices, emerging memory technologies, molecular electronics, CNT, optical interconnect, 3D integration, probabilistic computing, and spin logic.
b. Emerging Applications:
Multimedia, consumer electronics, communication, networking, sensor and sensor networks, ubiquitous computing, biologically-inspired computing, microfluidics, bioelectronics, and biomedical applications.
* ASP-DAC 2014 University LSI Design Contest encourages submitting original papers on LSI design and implementation at universities and other educational organizations. (Please see "Call for Designs" on the ASP-DAC 2014 web site.)
Submission of Papers:
Please read "Preparation Guide for Technical Paper Submission" carefully.
The key dates are as follows:
Deadline for submission: 5 PM JST (UTC+9) July 10 (Wed.), 2013
Notification of acceptance: Sep. 11 (Wed.), 2013
Deadline for final version: 5 PM JST (UTC+9) Nov. 11 (Mon.), 2013
All accepted papers must be presented by one of the authors. IEEE reserves the right to exclude a paper from distribution after the conference (e.g., removal from IEEE Xplore) if the paper is not presented at the conference. Please also note that ASP-DAC will work cooperatively with other conferences and symposia in the field to check for double submission.