Oasys Announces Parallel Equivalency Checking

Performance Scales Linearly with the Number of Processors Used

SANTA CLARA, Calif. — (BUSINESS WIRE) — May 13, 2013 — Oasys Design Systems announced today the immediate availability of Oasys RealTime Parallel EC (equivalency checking).

“Oasys engineers started with a production proven EC technology then raised the bar in 3 dimensions – speed, scalability and simplicity – over competing products to create a truly compelling solution for synthesis verification,” stated Scott Seaton, President and CEO at Oasys. Hierarchical support, automatic partitioning and parallel multi-processing technology enable simultaneous verification of sub-blocks, providing performance that scales linearly with the number of processors. The hierarchical top down approach also provides the capacity to perform equivalency checking on an entire chip at once. Integration with Oasys RealTime synthesis makes RTL to gate level EC for synthesis verification as simple as pushing a button.

“To give an idea of the type of performance Oasys RealTime Parallel EC can deliver. It verified a 4.7 million instance design in approximately 2 hours using 10 processors,” stated Paul Van Besouw, CTO at Oasys. For more information on Oasys RealTime Parallel EC, including benchmark times for various size designs utilizing different numbers of processors click here.

Oasys RealTime Parallel EC is available immediately as an add-on option to the Oasys RealTime suite of design for implementation (DFI) tools.

About Oasys Design Systems

Oasys Design Systems is a private electronic design automation (EDA) supplier specializing in design for implementation (DFI) tools which ensure RTL is ready for implementation. Oasys corporate headquarters is located at 3250 Olcott Street, Suite 105, Santa Clara, Calif. 95054. Telephone: (408) 855-8531. Facsimile: (408) 855-8537. Email: Email Contact. For more information, visit: www.oasysdesign.com.


Oasys Design Systems
Scott Seaton, 408-855-8531 ext. 306
Email Contact

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