EdXact Exhibits at CDNLive EMEA in Munich


EdXact, provider of advanced software solutions that accelerate post layout design and verification is going to exhibit as a technical partner at the Designer Expo at CDNLive EMEA next week in Munich.


EdXact uses the occasion to exhibit its product families that have been build on a common analysis platform, Alps™.

  • Jivaro™, EdXact's netlist reduction engine allows to reduce the overhead of interconnect parasitic components on circuit simulation time with a very high degree of accuracy and efficiency. The tool name is derived from the tribe of Jivaro Indians in the Amazonas region. Their speciality is to shrink heads. Just as Jivaro shrinks netlists.

    Jivaro has a tight integration into Virtuoso. The interface into Virtuoso is branded Salsa.
  • Viso™, EdXact's circuit analysis tool provides fast analysis capabilities to the designer. Quickly verifying the resistance between ports, determining the cross-coupling between nets, estimating the delay, fast analysis of large arrays of PowerMOS devices, are typical tasks for Viso.
  • Belledonne™, EdXact's circuit comparison tool with emphasis on parasitics allows comparing quickly and accurately very large netlists in order to tune parameters of extraction tools, find differences between two versions of a design, increase robustness of design kits.


CDNLive EMEA brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.

About EdXact

Founded in 2004, EdXact focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with local sales offices in California, Japan, Korea and Taiwan. For additional information please visit: http://www.edxact.com

Or contact: Email Contact


Mathias Silvant,
President & CEO,
Tel.: +
Email Contact

Review Article Be the first to review this article
 True Circuits: Ultra PLL


Featured Video
Design Verification Engineer for intersil at Morrisville, North Carolina
Applications Engineer for intersil at Palm Bay, Florida
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise