HDL Design House Announces PCS IP Core

Belgrade, Serbia – March 12th, 2013 –- HDL Design House, provider of high performance digital and analog IP cores and SoC design and verification services, has announced availability of its Physical Coding Sublayer (PCS) IP core (HIP 500) which enables transmission and reception of data via 8-Lanes SerDes interface. It is able to multiplex a synchronous data stream over 8 Lanes, while guaranteeing data alignment and super-frame synchronization.

The PCS is responsible for generation of idle characters, lane striping and encoding on transmission and decoding, lane alignment and restriping on reception. The PCS uses an 8B/10B encoding for transmission over the link. The PCS IP Core provides two kinds of loopback capabilities, the external one that comprises 8B10B encoders/decoders only and internal that comprises both 8B10B encoders/decoders and super-frame generation/recovery.

For test purposes, the PCS IP offers built-in PRBS generator/verifier pairs. The PRBS pairs are implemented in two levels, the super-frame level and per-lane level.

About HDL DH FlexIP core library 

The FlexIP core library includes a broad portfolio of high-quality, silicon proven digital and analog IP cores for SoC designs. The library covers a large number of standards and protocols such as HDMI, DisplayPort, MIPI (M-PHY, D-PHY, DSI, UniPro and CSI, DigRF, BIF), USF, I2S, Serial RapidIO, SPI flash memory controller, PCI Express, SATA, USB 3.0, and others. Apart from the large number of supported protocols and standards, one of the greatest competitive advantage for users of the FlexIP core library is HDL Design House outstanding capabilities in providing integration services, customization of the IP core at customer's request, verification solutions for the given IP core, as well as on site support. For more information on the FlexIP core library, please go to http://www.hdl-dh.com/products.html 

About HDL Design House 

HDL Design House delivers leading-edge digital and analog design and verification services and products in numerous areas of SoC and complex FPGA designs. The company also develops IP cores and offers back-end services. The company has extensive experience with the ARM CPU architecture, ARM CPU processor interfaces and development or integration of SoC based on ARM CPU. Founded in 2001 and currently employing 60 engineers working in two design centers in Serbia, HDL Design House mission is to deliver high quality products and services, with flexible licensing models, competitive pricing and responsible technical support. The company was awarded ISO 9001:2000 and ISO 27001:2005 certifications in December 2006/2009. For more information, please visit www.hdl-dh.com 


Contact:

Milena Jovanovic
Marketing Manager
HDL Design House
Phone: +381 (0) 114145557
Email Contact 




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