Users Reduce Risk in Three Main Areas, Providing Verification Previously Impossible
March 06, 2013 -- Coupling Wave Solutions S.A. (CWS), a leader in solutions for noise analysis in complex A/MS SoC designs, announced that STMicroelectronics has adopted the WaveIntegrity™ analysis tools to remove risk caused by on-chip, package and PCB parasitics. Following multiple evaluations, covering use for both CMOS and FD-SOI processes, a leading contender for next-generation low-power products fabrication, STMicroelectronics is deploying WaveIntegrity across groups designing complex IP, Digital Convergence Products and Automotive devices.
CWS has worked closely with STMicroelectronics to ensure its teams have full visibility of potential noise issues in their IP and SoC designs. As a result, STMicroelectronics users of WaveIntegrity benefit from a proven, flexible and highly differentiated verification solution.
“Minimizing power while maximizing performance and securing functionality is driving STMicroelectronics’s adoption of new tools and methodologies. The comprehensive CWS noise analysis solution has enabled our teams to successfully identify and avoid significant noise issues in mixed-signal SOCs,” said Philippe Magarshack, STMicroelectronics Executive Vice President. “The close and ongoing cooperation with CWS is helping our teams achieve success with next-generation designs incorporating advanced analog and digital IPs, across a range of processes, including our latest advances in FD-SOI.”
STMicroelectronics has used WaveIntegrityTM to analyze 28nm FD-SOI SOCs, minimize power-supply bumps and pin count, analyze digital noise on I/Os in 55nm CMOS automotive designs, and ensure mixed digital and RF ICs are clean of noise issues, at 40nm and below. This has required the development of methodologies appropriate to the specific requirements of each type of design, as well as the wider adoption of more “standard” techniques enabled by WaveIntegrity.
“The complexity and frequency of SoC designs increase year-on-year, together with increasingly stringent power requirements. Successfully verifying the noise characteristics of the SoCs, the package they are placed in and the PCBs they are inserted on, has become an increasingly difficult challenge: applying “rules of thumb” is no longer adequate. The capabilities of WaveIntegrity provide and support such analysis, and enable verification previously considered impractical by other means,” commented Brieuc Turluche, president and CEO of CWS. “With multiple teams contributing to each design it is essential that noise analysis is both easy and rapid to implement at each stage.”
To learn more visit www.cwseda.com.