Media Advisory: Atrenta to Participate in Formal Verification, Energy Efficiency and 3D Sessions at DATE 2013

San Jose, CA – March 5, 2013

What:

Session: Abstraction Techniques and SAT/SMT-Based Optimizations

When:

Date: Thursday, March 21, 2013

Time: 11:00 a.m. – 12:30 p.m.

Location / Room: Chartreuse

Who:

Session chair(s):

Fahim Rahim - Atrenta, France
Co-chair: Julian Schmaltz - Open University of the Netherlands, NL

Why:

Automatically computing abstractions of large circuits combined with powerful SAT and SMT solvers is key to the success of formal verification techniques. The papers of this session present significant improvements in abstraction techniques and SAT/SMT-based optimizations.

Details about the session:

http://www.date-conference.com/conference/session/10.4

******************************************************

What:

Paper: Fast and Accurate Methodology for Power Estimation and Reduction of Programmable Architecture

Who:

Erwan Piriou and Raphael David - CEA LIST, Fance

Fahim Rahim - Atrenta, France

Solaiman Rahim - Atrenta, US

When:

Date: Wednesday, March 20, 2013

Time: 5:15 p.m. – 5:30 p.m.

Location / Room: Meije

Why:

This paper presents a power optimization methodology that provides a fast and accurate power model for programmable architectures. The approach is based on a new tool that estimates power consumption from a register transfer level (RTL) module description, activity files and library. It efficiently provides an instruction-level accurate power model and allows design space exploration for the register file. A 19% improvement for a standard RISC processor is demonstrated.

Details about the session:

http://www.date-conference.com/conference/session/8.5

 

******************************************************

What:

Panel: 2.5D vs. 3D: Who is Winning and Why?    

When:

Friday, March 22, 2013

Time: 3:40 p.m. – 4:40 p.m.

Location / Room: Bayard

Who:

Paul Franzon - University North Carolina, US

Georg Kimmich - STEricsson, France

Juan Rey - Mentor Graphics, US

Ravi Varadarajan - Atrenta, US

Why:

3D Integration is a promising technology for extending Moore's momentum in the next decennium, offering heterogeneous technology integration, higher transistor density, faster interconnects, and potentially lower cost and time-to-market. To produce 3D chips, new capabilities are needed: process technology, architectures, design methods and tools, and manufacturing test solutions. The goal of this Workshop is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, in order to update each other on the latest state-of-the-art, exchange ideas, and discuss future challenges.

 

Details about the session:

http://www.date-conference.com/conference/workshop-w5

******************************************************

 

About Atrenta

Atrenta’s SpyGlass® Predictive Analysis software platform significantly improves design efficiency for the world’s leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today’s consumer electronics revolution. More than two hundred companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. SpyGlass functions like an interactive guidance system for design engineers and managers, finding the fastest and least expensive path to implementation for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence.   www.atrenta.com 

For more information, contact:

Atrenta:
Charu Puri
Tel: +1-408-453-3333
Email: Email Contact

PR Agency:
Lee PR
Liz Massingill  ( Email Contact)
Tel: +1-650-363-0142




Review Article Be the first to review this article
Featured Video
Jobs
Technical Support Engineer for EDA Careers at Freemont, CA
Senior DSP Architect / System Engineer for General Dynamics Mission Systems at Scottsdale, AZ
FAE FIELD APPLICATIONS SAN DIEGO for EDA Careers at San Diego, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
SOC Logic Design Engineer for Global Foundaries at Santa Clara, CA
Upcoming Events
FPGA 2017 at 350 Calle Pincipal, Marriott Hotel Monterey CA - Feb 22 - 24, 2017
DVCon 2017 Conference at DoubleTree Hotel San Jose CA - Feb 27 - 2, 2017
IoT Summit 2017 at Great America ballroom, Santa Clara Convention Center Santa Clara CA - Mar 16 - 17, 2017
SNUG Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Mar 22 - 23, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy