India SystemC User Group Conference (ISCUG)
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  System Level timing and power estimation techniques using SystemC
Philipp A. Hartmann 
  
SystemC and TLM-2.0 based ESL methodologies are widely used for early application, platform, and performance analysis already.  But the consideration of an embedded device's power consumption and its management is increasingly important nowadays, not only for mobile devices.  Currently, it is not equally easily possible to integrate such extra-functional information at electronic system-level. In this talk, the design challenges of today's heterogeneous HW/SW systems regarding power and complexity, both for platform vendors as well as system integrators are discussed.  Existing and new approaches for system-level timing and power estimation techniques, as well as their efficient integration into SystemC/TLM virtual prototypes are presented.  To enable interoperability beyond timing and functionality, the need for future standardization efforts in the area of extra-functional properties is motivated.
  
Philipp A. Hartmann is a senior researcher and project manager in the Hardware/Software Design Methodology group at OFFIS Institute for Information Technology, Oldenburg, Germany. He obtained his diploma degree (Hons) in Computer Science from University of Bonn, Germany. His research interests include SystemC-based design methodologies, fast simulation models, and automated model refinement. Being a SystemC user for more than ten years, he has contributed to IEEE 1666-2011 (sc_vector) and is an active member of the ASI SystemC Language, TLM and CCI Working groups. As part of these activities, Philipp has been part of the core developer team that prepared and refined the latest 2.3.0 release of the ASI SystemC proof-of-concept implementation.
 

 

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India SystemC User Group Conference (ISCUG) 
 
 
 
A platform to discuss the SystemC based next generation methodologies for design and verification of Electronics Systems (Semiconductor Chips + Embedded Software)
  
Venue: Hotel Radisson, Noida, India
Tutorial Day: 14th April, 2013 (Sunday), Conference Day: 15th April, 2013 (Monday)

Register for the event online at: http://iscug.in/event_registration . Early bird discount ends on 28th Feb, 2013
To receive regular updates about the event, register your mail id at www.iscug.in, and Like us on Facebook
  
  About ISCUG
 
The Indian SystemC User's Group (ISCUG) organization aims to accelerate the adoption of SystemC as the open source standard for ESL design. ISCUG provide a platform to share the knowledge, experiences and best practices about SystemC usage. ISCUG organize an annual conference which provides a platform for the SystemC beginners, the SystemC experts, ESL managers and the ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The event will also be attended by following target audience:
  • SoC Architects involved in architectural exploration, performance optimization, power optimization
  • Embedded software engineers who want to explore usage of Virtual Platforms for embedded software development
  • Chip verification engineers who want to explore SystemC based verification methodologies
  • Chip design engineers who want to explore SystemC as the language for chip design at abstraction level higher than RTL

The event is designed on the pattern of similar events happening worldwide: NASCUG, ESCUG, Japan SystemC Forum etc.. 

  Participate
  

Abstract submission date extended to 28th Feb. Submit your abstract at www.iscug.in 
The abstract will be reviewed by the technical review committee, they reserves the right to make final decision on selection of the speaker.
  
Conference Day
  • Full day of Technical Presentations, Keynote speech, Invited talks
  • Display booths: Innovative technologies displayed by sponsor
Tutorial Day
  • First Half (Before Noon): SystemC & TLM2.0 Introductory Tutorial
  • Second Half (After Noon): Three tracks in parallel
    • Advanced modelling techniques
    • High level synthesis using SystemC. Raising the abstraction of chip design above RTL
    • SystemC based verification methodologies
  
   Confirmed Speakers
  
AtulKwatra

Atul Kwatra,

Principal Engineer, Intel

PhilippHartman
Philipp A. Hartmann,
Sr. Researcher, OFFIS
   
Dennis Brophy,
Vice Chair, Accellera Systems Initiative
Mike Meredith
Vice Chair, Accellera Synthesis WG
  
  
   Affiliations
  
    
 
  
Sponsors
      
  
For sponsorship opportunities, contact: Email Contact , +919811204168
This email was sent to sanjay@edacafe.com by Email Contact |  
ISCUG | ISCUG | Noida | India



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