Aldec offers Advanced Screening of Functional Verification Platform’s Latest Release at DVCon 2013

Henderson, NV – February 26, 2013 –  Aldec, Inc., joins other top tier functional design and verification exhibitors at The Design & Verification Conference & Exhibition (DVCon), February 25-28, 2013 in San Jose, California.

“With its consistent focus on delivering the latest information from the leading edge of technology, standards and methods, DVCon continues to serve as an important platform to bring new solutions market,” said Christina Toole, Aldec Marketing Manager, “We are pleased to be back in San Jose again this year with an advanced preview of our latest solutions.”

Advanced Verification

Aldec will offer an early preview of the latest version of its functional verification platform, Riviera-PRO™, delivering solutions to verification challenges. Demonstrations will showcase the innovative tool suite, including requirement-driven design, simulation, and debugging for mixed-language and mixed-signal SoC and large-scale FPGA designs. The platform’s latest release includes significant enhancements for efficient application of Universal Verification Methodology (UVM), verification management and coverage closure with UCIS-compatible database, and mixed VHDL, Verilog-AMS, SystemVerilog, and SystemC designs.  www.aldec.com/products/riviera-pro 

Hardware-assisted Verification

DVCon attendees will also learn about the latest HES™ innovations. HES-DVM™ is Aldec’s complete ASIC/SoC hardware-based verification solution that provides a unified platform for bit level simulation acceleration, transaction level emulation, HW/SW co-verification, virtual modeling and prototyping.  www.aldec.com/products/hes-dvm

Free UVM and Assertions Online Training 

Aldec invites visitors to DVCon to tour Fast Track™ ONLINE, a convenient, online training portal that is available at no cost to the design verification community. The premiere training course for the new program is, Fast Track™ to UVM ONLINE, which introduces hardware designers familiar with Design Subset of SystemVerilog into the brave, new world of Universal Verification Methodology (UVM). Newly added, Fast Track™ to Assertions ONLINE,includes practical examples of assertions and covers presented side-by-side for VHDL (PSL) and SystemVerilog (SVA).  www.aldec.com/onlinetraining.

About DVCon

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. For more on Accellera, visit  www.accellera.org. For more on DVCon, visit  www.dvcon.org.

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.  www.aldec.com


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact: Christina Toole, 
Aldec, Inc. 
+(702.990.4400)
Email Contact



Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Qualcomm’s Lu Dai: Energetic leadership for Accellera
More Editorial  
Jobs
SOC Logic Design Engineer for Global Foundaries at Santa Clara, CA
Sr. Staff Design SSD ASIC Engineer for Toshiba America Electronic Components. Inc. at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Principal Engineer FPGA Design for Intevac at Santa Clara, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Upcoming Events
IoT Summit 2017 at Great America ballroom, Santa Clara Convention Center Santa Clara CA - Mar 16 - 17, 2017
SNUG Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Mar 22 - 23, 2017
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy