Real Verification Newsletter February 2013

Real Intent December 2012 Verification News


February 2013

3 New Software Updates, DVCon Panel + Tutorial, Calypto News

2013 is starting with a wave of announcements.  We had new releases of the Ascent IIV, Ascent XV and Meridian Constraints products.  We have a large role at DVCon with a panel we organized and a joint tutorial with Calypto and DeFacTo. We announced the the integration of Calypto’s Catapult high-level synthesis tool and Real Intent’s Ascent™ Lint product. And one of our technologists is presenting both a paper and tutorial at ISQED. Details for all of these are below.

Thoughts From Prakash Narain, President And CEO…

You may have noticed a new verification paradigm – the growing symbiotic relationship between design and verification that makes it hard to tell where one leaves off and the other one begins. System-on-chip (SoC) verification now uses dynamic simulation and static timing analysis along with problem-specific verification. Combining multiple engines – structural analysis, targeted formal analysis, instrumented simulation and hierarchical processing – delivers the needed speed, capacity and accuracy. This mixing of verification engines lets you find bugs with much less effort, step by step, with lots of back and forth communication. For example, clock domain crossing verification requires a problem-specific method that combines multiple engines. Structural analysis analyzes the RTL in the context of the specific problem you’re solving, and scopes out the problem for formal. So there’s a nice relationship between structural and formal that we exploit all the time in our products, as you’ll see below. To learn more about accelerating advanced sign-off please look at the list of published articles on our web-site or the Real Talk Blog.

New Releases of Ascent IIV,  Ascent XV,  Meridian Constraints

Ascent IIV is a state-of-the-art automatic RTL verification tool. It finds bugs using an intelligent hierarchical analysis of design intent. No test bench is needed, making it easy and efficient to find RTL bugs earlier in the design flow before they become more expensive to uncover. The analysis minimizes debug time by identifying the root cause of issues and provides the VCD traces that show the sequence of events that lead to an undesired state. Our new release delivers 50% faster performance and features incremental analysis. Click here to read the announcement details.

Ascent XV identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. It enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level. Our new release delivers enhanced modeling of X’s that come from retention flops, a major source of X’s in a design, and an enhanced debug interface. Click here to read the announcement details.

Meridian Constraints is the best-in-class, comprehensive constraint management solution in the market. It offers high-performance constraint validation, template generation, coverage analysis, equivalence checking and timing exception verification capabilities designed to provide users with ultimate confidence in the timing constraints employed across all phases of the implementation flow. Our new release delivers enhanced speed, analysis and SystemVerilog language support. Click here to read the announcement details.

Design and Verification Conf. (DVCon) Panel + Exhibit, Feb. 26-28

DVCon 2013 is celebrating its 25th year at the Doubletree, Santa Clara , and Real Intent is there in full force with our usual exhibit plus:

•  A panel we organized, Where Does Design End and Verification Begin? on Wednesday, Feb. 27, 8:30 - 10 a.m. It explores the question, “Are design and verification completely entwined, or is there a boundary or clean hand-off between them?” The panel moderator is Brian Hunter of Cavium Networks, and panelists include John Goodenough (ARM), Oren Katzir (Intel), Harry Foster (Mentor), Pranav Ashar (Real Intent) and Gary Smith (GarySmithEDA).

•  A ½-day tutorial jointly with Calypto and DeFacTo, Pre-Simulation Verification for RTL Sign-Off on Thursday, Feb. 28, 1:30-5 p.m. Integrating heterogeneous IP and design units into an SOC requires confirmation of protocols, power budgets, testability and the correct operation of multiple interfaces and clock domain crossings (CDC). Although simulation could be used to fully test an SOC, complete RTL testing is too expensive for design teams. Instead, abstract modeling and pre-simulation static analysis of RTL have become imperative in SOC design flows.

The presentations will cover power exploration, analysis and optimization using an abstract model with high-level synthesis (HLS), followed by the RTL static verification for: syntax and semantic checking (lint); constraints planning and management; reset analysis and optimization; automatic intent verification; CDC sign-off; DFT analysis and insertion; and X-analysis and optimism/pessimism correction. Each step represents a substantial hardening of the design and is best served by a top-of-the-line tool designed specifically for that step.

Calypto’s Catapult Integrates with Real Intent’s Ascent Lint

The joint solution ensures Catapult-generated RTL code is lint-clean and error-free for a safe and reliable implementation flow from RTL to GDSII layout.  Click here to read the announcement details.

ISQED Symposium, Mar. 4-6, 2013 at TechMart in Santa Clara, Calif.

Dr. Vinod Viswanath, Senior Member Technical Staff at Real Intent, participating with Intel Corp. and University of Texas Austin, will present a tutorial and a paper at this year’s International Symposium on Quality Electronic Design (ISQED).

The tutorial, Holistic Power Management: The Future of Handhelds and other Low Power Devices , will be presented with Intel technologists from 4:50-6 p.m. on Mar. 4. It covers a trend to maximize power optimization, and delves into power efficiency as a growing concern for all aspects of computing systems – from very small, highly integrated SoC-based handheld devices to larger systems including servers and many-core high-performance computing systems.

Viswanath also will present a joint paper, On a Rewriting Strategy for Dynamically Managing Power Constraints and Power Dissipation in SoCs (systems-on-a-chip), at 2:30 p.m. on Tuesday, Mar. 5 with experts from Intel Corp. and University of Texas Austin. It covers a novel and highly automated technique for dynamic system-level power management of SoC designs.


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