Tensilica Unveils IVP - A New Imaging/Video DSP IP Core for Mobile Handsets, DTV, Automotive and Computer Vision Applications

IVP Offloads Host CPU While Providing a 10 to 20x Peak Performance Boost 

SANTA CLARA, Calif.  USA – February 12, 2013 –  Tensilica, Inc. today introduced IVP, an imaging and video dataplane processor (DPU) that is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisiosn (DTV), automotive, video games and computer vision based applications. The IVP DPU is a much needed breakthrough product in terms of energy efficiency and performance in current products and to enable applications never before possible in a programmable device.  IVP is supported by a network of third-party application developers who are actively porting leading-edge image applications to the IVP platform including innovative multi-frame image capture and video pre- and post-processing algorithms, as well as established, yet evolving, technologies such as video stabilization, high dynamic range (HDR) image, video HDR, object and face recognition and tracking, low-light image enhancement, digital zoom and gesture recognition. 

With its unique architecture tuned for imaging and video pixel processing that gives it peak performance of 10 to 20x most host CPUs, the IVP is capable of over 130 billion 16-bit RISC-equivalent operations per second. This allows IVP to tackle the complexity of new image, gesture and video algorithms which would be impossible to run on general-purpose host CPU architectures. It also provides 2 to 4x the performance of any merchant imaging DSP IP core on the market today.

“As mobile camera usage grows, so grows the demand for advanced video and imaging features, which must be offloaded from the host processor for the best performance at the lowest possible battery life,” stated Will Strauss, president of Forward Concepts and a leading DSP analyst. “Given the pace of innovation in image and video processing, the new IVP core should help Tensilica’s customers get efficient chips implementing proprietary algorithms to market much faster and with the added benefit of lowering the cost of changing those algorithms.”

“Consumers want advanced imaging functions like HDR, but the shot-to-shot time with the current technology is several seconds, which is way too long. Users want it to work 50x faster. We can give consumers the instant-on, high-quality image and video capture they want,” stated Chris Rowen, Tensilica’s founder and CTO. “The IVP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing, supporting increasing sensor resolutions. It is ideal for tomorrow’s exciting new products.”

Efficient Processor-based Architecture

Tensilica’s IVP is based on a 4-way VLIW (very long instruction word) architecture that delivers high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset. The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10 GBytes/second of throughput and local memory throughput of 1024 bits per cycle (sixty-four 16-bit pixels/cycle) to keep up with the rapid pace of resolution and frame rate requirements. The IVP also features many imaging-specific operations to accelerate 8-, 16- and 32-bit pixel data types and video operation patterns.

The IVP is extremely power efficient.  As an example, for IVP implemented in an automatic synthesis, place-and-route flow in 28nm HPM process, regular VT, a 32-bit integral image computation on 16b pixel data at 1080p30 consumes 10.8 mW.  The integral image function is commonly used in applications such as face and object detection and gesture recognition.

IVP’s high performance is demonstrated by complex algorithm kernels such as motion search and normalized cross-correlation, commonly used in high-precision block and feature matching and optical flow.  For a smart motion search on 16-bit data over a 1920x1080 frame with 256x16 pixel search range and 9x3 pixel block size, IVP can achieve a rate of 142 sums of absolute differences per cycle.  In addition, a normalized cross-correlation function on 16-bit pixel data with 32-bit accuracy achieves 1 million 8x8 blocks per second.

Software

Many companies have proprietary imaging and computer vision algorithms which can be implemented on the IVP, as it employs the C programming model common among all Tensilica DPUs. Tensilica has also created a partner network to enable availability of pre-ported, efficient third-party imaging software. Initial partner companies porting advanced imaging suites to the IVP DPU include Almalence, Irida Labs, Dream Chip Technologies and Morpho, Inc.

Tensilica’s state-of-the-art toolset enables easy programming of proprietary algorithms for higher performance and differentiation. “We were impressed with the ease of porting and optimizing our application to Tensilica’s IVP,” stated Eugene Panich, CEO of Almalence. “Tensilica’s compiler helped us achieve high performance and is among the best we’ve ever used. We were also  impressed with the quality of their entire toolset.”

“We were excited to partner with Tensilica to offer our embedded vision applications since the IVP offers so much performance compared to other platforms,” said Vassilis Tsagaris, CEO of Irida Labs.  “The power efficiency we’ve seen for our video stabilizer, for example, makes IVP the perfect offload engine for imaging.”

Customizable for Differentiation

Tensilica’s IVP DPU can be further customized using Tensilica’s patented processor-generation system. The DPU creation process is totally automated and fully supported by a matching software tool chain. The tool chain includes an optimized compiler, linker, assembler and debugger, plus a matching fast instruction set simulator. 

Availability

Early-access lead customers took delivery of IVP last year, and the IVP DPU is available for broad licensing now.

About Tensilica

Tensilica, Inc. is the leader in dataplane processor IP cores with over 200 licensees. Dataplane processors (DPUs) combine the best capabilities of DSPs and CPUs while delivering 10 to 100x the performance because they can be optimized using Tensilica’s automated design tools to meet specific and demanding signal processing performance targets. Tensilica’s DPUs power SOC designs at system OEMs and seven out of the top 10 semiconductor companies for designs in mobile wireless, telecom and network infrastructure, computing and storage, and home and auto entertainment. Tensilica offers standard cores and hardware/software solutions that can be used as is or easily customized by semiconductor companies and OEMs for added differentiation. For more information on Tensilica’s patented, benchmark-proven DPUs visit  www.tensilica.com.




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