DLIN, Local Interconnect Network IP Core [not only] for automotive

The DLIN is the newest Local Interconnect Network IP Core developed by Digital Core Design. Polish IP Core provider has presented a solution, which is fully compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium. The core is described at RTL level, empowering the target use in both, FPGA and ASIC technologies.


Bytom, 1st of February, 2013. The DLIN, DCD’s IP Core for Local Interconnect Network, is an ideal solution most of all for automotive designs. As technologies and facilities implemented in a car grow every year, the need for a cheap serial network has arisen. That’s why LIN seems to be the most suitable solution to integrate intelligent sensor devices or actuators in today’s cars. Contrary to the CAN, it enables cost competitive serial communication, building the same an extended vehicle’s electrical network, which… will be used as CAN’s sub-network.  – Our DLIN controller supports transmission speed between 1 and 20kb/s – says Jacek Hanke, CEO in Digital Core Design – that allows to transmit and receive LIN messages compatible to LIN 1.3, LIN 2.1 and also the newest LIN 2.2 rev A.

Compared to the CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective. That’s why the DLIN is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. DCD’s IP Core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or as a slave LIN node, depending on a working mode determined by the microprocessor/microcontroller. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). DCD’s IP Core includes also a programmable timer, which allows to detect timeout and synchronization error. The Core is described at RTL level, empowering the target use in FPGA and ASIC technologies.

More information & data sheet: http://www.dcd.pl/ipcore/132/dlin/

DLIN presentation:    http://youtu.be/H72w8laPW5k

 

KEY FEATURES:

●       Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.

●       Automatic LIN Header handling

●       Automatic Re-synchronization

●       Data rate between 1Kbit/s and 20 Kbit/s

●       Master and Slave work mode

●       Time-out detection

●       Extended error detection

●       “Break-in-data” support

●       Available system interface wrappers:

●       AMBA - APB Bus

●       Altera Avalon Bus

●       Xilinx OPB Bus

 

 

 

 

 

 

 

 

 

 




Review Article Be the first to review this article
SI2

ClioSoft: Design Hub

Featured Video
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
Grant Pierce: Grand Challenges in IP
More Editorial  
Jobs
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
Upcoming Events
EMC PCB Design Integration at 13727 460 Ct SE North Bend WA - Jun 6 - 9, 2017
DAC 2017 Conference at Austin TX - Jun 18 - 22, 2017
2017 FLEX Conference at Monterey Conference Center 1 Portola Plaza, Monterey CA - Jun 19 - 22, 2017
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
NEC: CyberWorkbench
Verific: SystemVerilog & VHDL Parsers
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy