Five one-day seminars on signal integrity/high-speed digital design/EMI-EMC by Washington Laboratories

January 26, 2013 -- Five one-day seminars on signal integrity/high-speed digital design/EMI-EMC are being held by Washington Laboratories, Gaithersburg, Maryland, February 25 through March 1, 2013. Instructor is Robert Hanson, MSEE. Link is http://www.wll.com/academy and click on "High-Speed Digital Design Training" 2/25-3/1/2013 for details.  

FIVE ONE-DAY COURSES:
High-Speed Digital Design & EMI Control Training
  
Dates:
Feb 25 - March 1, 2013

Location:
Washington Laboratories Ltd.
7560 Lindbergh Drive,
Gaithersburg, MD 20879
301-216-1500
(Google Map)


 
The speed of today’s logic devices mandates that the interconnects on PCBs must meet the high switching rise/fall times of these devices. Switching edges are in the 200ps to 300ps range and some devices have edges that have reached the 17ps rate. This has resulted in high-speed design problems, such as:

• A lack of control over impedance and reflections
• Crosstalk and bypassing failures
• Time delays, false triggering, and reflections
• Failure to meet EMI and FCC requirements

 

It is the edge rate, not the frequency, that exacerbates this problem, so even if your design is for moderate frequency, the edge rates can cause these designs to reflect the high-speed effects.

Most designs today use a microprocessor and today’s micros have clock rates over 1000 times higher than the original 8- and 16-bit machines. A key factor is the minimization of the semiconductor device (now at 32 nm) leading to less parasitic L and C, and thereby faster switching rates. This phenomenon also is apparent in RAMs, ROMs, ASICs, and gate arrays. This leads to PCBs requiring terminators, new CAD routing disciplines, and component additions to minimize ground bounce effects. More and more designs are requiring these faster devices to meet more demanding specifications that match or beat the competition.

The following one-day courses are offered to cover the various aspects of high-speed digital design and EMI/EMC issues :

  • DAY 1. Transmission Lines (T.L.)
  • DAY 2. Crosstalk, Layer Stacking, Separating Analog/Digital Planes, and Terminations
  • DAY 3. Bypassing, Power Delivery, Vias, Connectors, and Buses
  • DAY 4. Differential Signaling and Clock Distribution Control
  • DAY 5. Key Issues for EMI/EMC: How to Design and Build a Compliant System

These courses provide participants with the tools for recognizing the problems with any proposed high-speed design. Design rules and design processes are taught that insure the PCB will function properly at the prototype stage. Emphasis is placed on cost-competitive design without sacrificing high-speed integrity.

The courses are intended for digital design engineers, design managers, test engineers, EMI/EMC engineers, IC digital logic designers, project managers of high-speed designs, communication engineers, and military digital engineers. No advanced math is required, although participants will find it helpful to bring a scientific calculator to the course. The material is presented at a technical level that provides experienced designers with information to design and lay out a high-speed PCB that meets signal integrity (SI) and EMI.

Each course may be taken on a stand-alone basis or combined as needed. While each subsequent course builds upon the previous instruction, participants may enroll in any course or combination.

 



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