Real Intent Verification News, Dec. 2012: New Ascent Lint 2.0 and Survey Results on CDC, X-prop, Constraints

Real Intent December 2012 Verification News
 


December 2012

New Software Releases, New Features, More Success

It has been a busy year at Real Intent! This issue of Real Verifcation News showcases new software releases with enhanced features, celebrates our record business year and shares our DAC 2012 Verification Survey results. 

Thoughts From Prakash Narain, President And CEO…

If you were to ask anyone anywhere in the world: “What is your most indispensable possession?” chances are they would say it’s their mobile phone or tablet. Everybody seems to be using these as an inexhaustible source of information and entertainment – both for their business and social lives. But doing phone calls, photos, videos, e-mails, Twitter, Facebook, games, GPS, and so many more things all on one tiny, portable, low-power package means that huge chunks of data need to be processed. And that puts a tremendous burden on SoC design verification teams. What once was a 10M-gate high-water mark now has surged to 100M or even 400M! The multiple-clock schemes needed to meet such aggressive low-power goals in mobile devices can result in a staggering 100-500+ clock domains that need to be analyzed with clock domain crossing (CDC) verification tools. Our Meridian CDC is the only software solution that enables complete CDC sign-off for SoC designs with more than 100M gates. And our Ascent Lint is the fastest (by 20-50x) and most accurate RTL lint solution available in the industry. Both products deliver the speed, capacity, efficient reporting and completeness that set the standard in the market-place. To learn more about accelerating advanced sign-off please look at the list of published articles on our web-site or the Real Talk Blog.

Ascent Lint V2.0 Adds 60 New Rules & Enhanced SystemVerilog Support

We’ve taken the industry’s fastest linter for clean RTL before simulation and synthesis to a new level. It adds 60 comprehensive rules including new FSM checks, while maintaining its analysis speed of 450M gates in less than one hour, with no need for hierarchical processing.

According to Michael Martin, director of engineering at Integrated Device Technology, "IDT is enjoying the advantages of the new Ascent Lint 2.0 release. Our comprehensive design rule-set is fully supported and it takes just a few minutes for runs to complete. The product is easy to use and debug is fast and efficient. Ascent Lint was easy to adopt into our production design flows and we really like the integration with the new Verdi3 debug platform from SpringSoft. For any issues we had, the technical support team at Real Intent was impressive.”

You’ll find more information about it at: www.realintent.com/products

DAC 2012 Verification Survey on CDC bugs, X-propagation, Constraints

Compared to last year’s survey, our DAC 2012 survey with 318 respondents produced some surprising and some not so surprising results.

  Surprising
  • Despite the economy, more than ½ of the design teams expected design starts within 3 months.
  • The vast majority were designs with < 50 clock domains (such as block level designs or commodity consumer electronics). But >10% would have 100-500+ clock domains.
  • Almost 90% of respondents were moderately or very concerned about X-issues.
  • 20% thought exception generation was a pain point for SDC timing.
  • About 1/3 of the respondents seek to adopt or change X-propagation technologies, and about  twice as many are concerned about X-optimism in RTL than about X-pessimism in gate-level netlists.
Not surprising
  • Tool performance has overtaken noisy reports as the top issue for CDC and Lint tools.
  • Capacity has risen from negligible to almost the same level as noisy reports.
  • CDC bugs are affecting schedules; CDC verification is a sign-off criterion for most designs, although the percentages are somewhat lower than last year’s survey results.
  • Design teams need better verification to stop CDC bugs that slip through and cause late ECOs.
  • Constraints checking is the main issue for SDC timing constraints.

See full details about our survey on DeepChip.com and read how we meet the verification needs of SoC design teams.

New “Look And Feel” And New Headquarters Location in Sunnyvale, CA

Have you noticed our new look? We’ve redesigned our logo and Web site in a bold, contemporary style that mirrors the real intent of our EDA software offerings – accelerating advanced sign-off with precision, speed, ease and completeness. The familiar white and blue logo now is recast with striking simplicity. A vibrant blue arc directs the eye to crisp uppercase “REAL INTENT,” now in italics to create its own momentum. And that’s the point. SoC designers using our RTL solutions can quickly and easily achieve what they set out to do for SoC designs – ensure early functional verification as well as sign-off for timing constraints and clock-domain-crossing (CDC). In parallel, we’ve transformed our Web site to showcase Real Intent’s evolutionary change since our beginning as a formal verification company. We now have become instead a best-in-class verification application company – one that supports huge capacity with 5x-20x better performance than other solutions, and produces low-noise error reports organized for quick and easy debug. Finally, to accommodate our growth, we’ve moved to new offices. You’ll find us at the same e-mail and phone numbers, but the new street address is 990 Almanor Ave., Suite 220, Sunnyvale, CA  94085. Check it all out on our web site realintent.com.



Seasons Greetings!

Happy Holidays from
Real Intent

_________________________


New Headquarters
990 Almanor Ave., Suite 220
Sunnyvale CA



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