Synopsys Insight Newsletter: Featuring Video on Synopsys' Verification Strategy and the latest on DDR4 and HAPS-70

Issue 04, 2012
Customer Highlight
Using Advances in Synthesis Technology to Cut Implementation Time
Small-geometry effects can undermine design productivity and offset the integration benefits of SoCs unless these effects are accounted for during RTL synthesis. In this article, experts from IDT and Synopsys discuss how innovations in Design Compiler Graphical have minimized design iterations and cut implementation time at IDT.
Technology Update
The Past, Present and Future of DDR4 Memory Interfaces
Learn about the challenges designers face when making the step up to DDR4, and how Synopsys’ IP solutions will help them to transition to the latest JEDEC standard for commodity DRAM.

Accelerate Software Development with High-Performance FPGA-based Prototyping
Today’s ASIC and SoC design teams face challenges of short delivery schedules and high risk of chip defects. With the release of HAPS-70, a tightly integrated hardware plus software tools solution, Synopsys’ FPGA-based prototyping solution enables faster pre-silicon software development and better system-level validation from IP individual blocks to complete SoCs.

Complete Audio Solutions with ARC Processors
As consumers demand higher quality sound from their devices, the audio software that design teams use is becoming increasingly important. Learn how Synopsys’ SoundWave Audio Subsystem is enabling developers to benefit from certified code for audio processing and what this means for the end users.

Improving Compute Farm Efficiency for EDA
As chip complexity and schedule pressures grow, ensuring server farms have adequate CPU and memory resources for timely and successful job execution is critical. Learn how Adaptive Resource Optimizer (ARO) can assist design teams to make better use of all of their available compute resources.
Executive Insights
Accelerating SoC Verification
In this video interview with George Zafiropoulos and Michael Sanie, hear about Synopsys’ solution for SoC designers as well as Synopsys’ verification strategy with the recent SpringSoft and EVE acquisitions.
Synopsys Innovation Update
Latest News on Products, Technologies, Services and Solutions to Help Accelerate Innovation
Learn about some of the recent innovations Synopsys is providing its customers to help accelerate the development of better products sooner and more cost effectively.
Standards Column
OpenStand™: Measuring up in Design Automation Standards
With the recent public introduction of the Modern Standards Paradigm, OpenStand, Yatin Trivedi, director of standards and interoperability programs at Synopsys, shares his perspectives on how closely the design automation community follows these principles.
Special Announcement
Ace the Verification of Multicore SoCs
Learn how using the right VIP can help engineers to quickly and efficiently verify complex multicore systems that incorporate cache coherency based on the ARM® AMBA® ACE™ protocol.
Executive Insights Video

Accelerating SoC Verification Accelerating SoC Verification
SNUG Keynote Videos

SNUG Keynote Videos Aart de Geus Aart de Geus on Critical Mass, Systemic Complexity and Innovation


3dFinFet New structure... video Dr. Chenming Hu on 3D FinFET – New Structure Extends the Life of the Transistor!


John Cornish on Partnering... John Cornish on Partnering for Low Power
Recent Articles

FinFET: The Promises and the Challenges

Achieving Faster Design Closure with Early RTL Exploration

Next-Generation Xilinx FPGA Flows

Past Issues

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