DAC 50 Designer/User Track: Call for Submissions
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Submission is Quick and Easy!

1. Submit Slides By:

    February 6, 2013


2. Accept/Reject Notification:

    March 18, 2013


3. Present at DAC!


    All accepted submissions will be presented as posters and/or oral presentations

Submission Guidelines

SLIDE 1: Title and Authors


SLIDE 2: Author Details

Detailed author information


SLIDE 3: Abstract

1-2 Paragraph abstract


SLIDES 4-17: Details

Include speaker notes for Program Committee evaluation




About DUT

DUT Chair:

Robert Jones, Intel Corp.



Email: Email Contact



View 2011 and 2012 examples  HERE




Call for Submissions

The Designer/User Track (DUT) focuses on practitioners: designers, embedded software developers, and application engineers. The DUT aims to illustrate both benefits and challenges of tool usage, and provides educational and networking benefits for both end-users and tool developers.


NEW Easy Submission Process!


This year, instead of two submission rounds, there will be a single submission round. Authors will submit their work in the form of a slide deck suitable for a presentation at the conference. Accepted submissions will present a poster at DAC. Authors of particularly high-quality submissions will be invited to present their work as a talk during a regular DUT session.


Please visit the Designer/User Track page on the DAC website for more information on the submission process, and topic categories.


View the Designer/User Track Call for Contributions Publicity Flyer


D1. Embedded Systems and Software

  • Design reports and case studies
  • Architectural exploration, design, and optimization
  • Software specification, models, and framework
  • Security for embedded systems and software
  • Validation and verification
  • Design methodologies and flows

D2. Silicon Design (Front-End)

  • System and high-level hardware synthesis
  • Power/area/performance trade-offs and low-power design
  • Bus and network communication
  • Logic simulation
  • Validation, test planning, and coverage
  • FPGAs and emulation
  • Formal verification

D3. Silicon Design (Back-End)

  • Physical synthesis tools and techniques
  • Floorplanning
  • Timing and circuit analysis; circuit optimization
  • Reliability
  • Interconnect simulation and analysis
  • Physical design and manufacturability
  • Manufacturing test and silicon debug
  • Analog, mixed-signal, and RF design
  • Custom, standard cell, and FPGA design flows
  • Tool control and integration


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