SuVolta Announces Circuit-Level Performance and Power Advantages of DDC Technology at IEDM

LOS GATOS, CA -- (Marketwire) -- Dec 10, 2012 -- SuVolta, Inc., a developer of low-power CMOS technologies, today announced silicon results that demonstrate the performance and power advantages of its Deeply Depleted Channel™ (DDC) technology. The results are based on analog and digital logic circuits designed with SuVolta's PowerShrink™ low-power CMOS platform implemented in Fujitsu Semiconductor Limited's 65 nanometer (nm) low-power process. The results will be presented in a SuVolta-Fujitsu Semiconductor jointly-authored paper at the International Electron Devices Meeting (IEDM) being held in San Francisco beginning on December 10.

"The IEDM paper results confirm that Fujitsu Semiconductor's DDC-enabled process offers the best combination of performance and reduced power consumption of any 65nm or 55nm process," said Dr. Haruyoshi Yagi, corporate senior executive vice president at Fujitsu Semiconductor Limited. "The integration of the DDC technology into Fujitsu Semiconductor's low-power process has met all of our expectations. The DDC-based technology is expected to be commercially available in the first half of 2013 in a 55nm process offering."

The companies compared the same circuits fabricated in Fujitsu Semiconductor's standard process and using the DDC technology. Among other benefits, the companies will demonstrate the DDC technology provides approximately 30 percent performance increase in digital circuits at matched power when using a supply voltage (VDD) of near 1.2V. The companies will also demonstrate a 47 percent power reduction at matched performance when running the DDC technology with a 0.9V VDD. The DDC device parameters leading to the power and performance improvements include global and local threshold voltage (VT) variation improvement, higher body coefficient, and higher effective drive current (IEFF).

Fujitsu Semiconductor is SuVolta's first licensee of the DDC technology. Since the collaboration was announced in June 2011, the companies have worked together to bring up the DDC technology at the 65nm and 55nm nodes. At the 2011 IEDM conference, the companies presented low-power operation of SRAM (static random access memory) blocks down to 0.425V supply voltage by integrating the DDC technology into Fujitsu Semiconductor's low-power process technology. At this year's IEDM conference, SuVolta will present silicon results that demonstrate that the DDC technology enables either higher speed operation or lower power operation, depending on design requirements. Benefits include:

  • Ring oscillator (RO) circuits having nearly 50 percent reduction in active power dissipation at matched frequency and approximately 30 percent improved performance at matched power
  • Global threshold voltage (VT) variation improved by one-sigma
  • Up to 80 percent higher effective current (IEFF) at low supply voltages (VDD)
  • Design corner pull-in achievable through appropriate biasing
  • Operational transconductance amplifier (OTA) circuits having 12dB gain improvement despite lower supply voltage
  • Improved matching both locally and globally in current mirrors

"We are extremely pleased that parts built with Fujitsu Semiconductor's DDC-based 55nm process will soon be available," said Bruce McWilliams, president and CEO at SuVolta, Inc. "By enabling significant performance increases and up to 50 percent power reduction, SuVolta is providing the industry with a flexible and cost-effective device technology option, extending the benefits of CMOS technology."

The 2012 International Electron Devices Meeting (IEDM) will be held at the Hilton San Francisco Union Square, in San Francisco, California, from December 10-12. The SuVolta-Fujitsu Semiconductor jointly-authored paper will be presented on Tuesday, December 11, in session 14.4 entitled "A Highly Integrated 65nm SoC Process with Enhanced Power/Performance of Digital and Analog Circuits." For more information, visit

About SuVolta, Inc.

SuVolta, Inc. develops and licenses scalable semiconductor technologies that enable a significant reduction in IC power consumption while maintaining performance. Based in Silicon Valley, the team includes world-class engineers and scientists with a long history of technology development and innovation to advance the semiconductor industry. The company is backed by leading venture capital firms Kleiner Perkins Caufield & Byers (KPCB), August Capital, NEA, Bright Capital, Northgate Capital and DAG Ventures. For more information, visit

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