Dolphin Integration first to achieve 0.84 pA per bit in SpRAM at the 90 nm uLL embedded flash process

Grenoble, France -- Dec. 7, 2012 -- Dolphin Integration announces that the memory architecture RHEA, achieving leakage as low as 0.84 pA/bit at 90 nm uLL embedded flash process has now passed the pre-silicon assessment criteria (Level 1) of TSMC’s stringent IP9000 qualification program.

“We are happy to announce that the SpRAM RHEA generator is now available free of charge, for all TSMC 90 nm uLL process users. The RHEA architecture not only provides the best combination of density and leakage, but also features the capability to operate down to 1.0 V ± 10% at the 90 nm uLL process. This is the right SpRAM architecture to meet the challenging needs of MCUs in automotive, consumer and industrial applications”, said Elsa BERNARD-MOULIN, Dolphin Integration Marketing Manager for Libraries.

Dolphin Integration plays up the benefits of moving down to a 90 nm uLL process node:

  • Storage capacity of more than 800 kbits/mm2
  • Access time of 195 MHz for a 4k x 32 memory cut RHEA
  • Equivalent leakage at 90 nm uLL versus 180 nm uLL thanks to source biasing implementation and a mix of HVT and SVT MOS, together with dynamic power consumption divided by 3

Availability

The SpRAM RHEA Generator is "Foundry Sponsored".

For more information about this product, feel free to download the Presentation Sheet or to contact Dolphin’s Library Marketing Manager at Email Contact

To request a free access to the FE generator for evaluation purpose or to the BE generator for integration, please click here.




Review Article Be the first to review this article
Aldec

Featured Video
Jobs
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, PA
Applications Engineer for intersil at Palm Bay, FL
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, CA
Design Verification Engineer for intersil at Morrisville, NC
Upcoming Events
DVCon US 2018 at Double Tree Hotel San Jose CA - Feb 26 - 1, 2018
5th EAI International Conference on Big data and Cloud Computing Challenges at Vandalur, Kelambakkam high road chennai Tamil Nadu India - Mar 8 - 9, 2018
DATE '18: Design, Automation and Test in Europe at International Congress Center Dresden Ostra-Ufer 2 Dresden Germany - Mar 19 - 23, 2018
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL



Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise