New Seminar Presentations Available

This past October, ANSYS and Apache introduced our latest electronics design technology and simulation breakthroughs that help design next-generation electronics products in a four city seminar series. Presentations topics covered 20nm Low-Power IC Design, Signal Integrity/Chip-Package-System, and Antennas and RF.

If you missed these technical seminars, you can now view the presentations.  Click here.

Apache Design’s simulation software platforms and methodologies were honored by TSMC with a “Partner of the Year 2012” award for joint delivery of TSMC’s 20nm Reference Flow. This recognition emphasizes Apache’s advanced analysis and optimization technologies and close collaboration with TSMC for the delivery of their 20nm reference flow.

• Read the full  Press Release

ANSYS and Apache also announced that their simulation tools have been selected for TSMC’s 20nm Reference Flow and Chip on Wafer on Substrate (CoWoS) Reference Flow to meet power, noise and reliability requirements for ensuring timely and successful tape-out results.

• Read the full  Press Release

This Educast will provide useful information regarding how PowerArtist Calibrator and Estimator (PACE) and RTL Power Models (RPM) can improve the accuracy of your RTL power estimation prior to the availability of physical implementation and manage power delivery network integrity early in the process for cost-effective IC and package design decisions.

To register and watch the Educast,  click here.

For Apache's online Customer Support center, click here to register.

• CSIA-ICCAD 
  Chongqing, China
  December 6 - 7, 2012
• ARM Technology Symposium 
  Paris, France
  December 13, 2012
• VLSI Design
  Pune, India
  January 5 - 10, 2013
• DesignCon
  Santa Clara, CA
  January 29 - 30, 2013

• Apache on Signal Integrity
• Apache's RTL Power Model Named in EDN Hot 100 Products of 2012
• The Growing Integration Challenge
• New Incentives For Lowering Power
• Power Trumps Performance In Mobile Design
• Power and Reliability Challenges
• A User Study of Apache PowerArtist RTL Power Reduction Techniques
• Simulating Quality, Cost, and Schedule
• Why the Best-In-Class will Thrive in the New Defense-spending Environment

• Optimizing Cost-Performance-Schedule with Chip-Package-System Methodology
• ANSYS and Apache Technologies for an Integrated Chip-Package-System Flow
• Advanced Modeling for Chip, Package, System Co-analysis/Co-optimization
• Electronic Power and Thermal Management
• RTL Design-for-Power (DFP) Methodology
• Low Power Design Analysis
• Power and Noise Integrity for Analog/Mixed-Signal Designs
• PathFinder™: Solution for Full-chip IC ESD Integrity
• Power and Signal Line EM Design and Reliability Validation Challenges
• Technologies for Power, Signal, Thermal, and EMI Sign-off

To download these White Papers and other valuable resources from our website,  click here. Valid account required for some material.