Prosilog selects Avertec's HiTAS to qualify Memory Controller IPs

Paris, France- February 11, 2004- Avertec today announced that Prosilog has chosen HiTAS, Avertec's innovative timing platform, to characterize and qualify its DDR memory Controller family. Prosilog provides a family of multi-channels DDR-SDRAM memory controllers. These controllers are used to share between different subsystems the access to an external DDR memory.

"With this kind of design, there are a lot of asynchronous events and signal stability issues around the different interfaces. HiTAS from Avertec gives us the capability to quickly characterize our IP in a very accurate way over different technology processes" says Cyril Spasevski, project manager of Prosilog. "The timing analysis provided by HiTAS allows us to improve the performance of the arbitration scheme between the channels of the memory controller."

About Prosilog
Prosilog SA is a privately held company founded in November 2000, with offices in Cergy-Pr馥cture, near Paris, France. The company develops innovative RTL and system level design EDA tools, as well as soft IP cores to help SoC designers reduce the product design cycle. Prosilog provides solutions to automate the design and verification phases of SoC design. Prosilog SA is a member of the EDA consortium, the Virtual Socket Interface Association (VSIA), the Open SystemC Initiative (OSCI), as well as a member of the system level design working group in the Open Core Protocol International Partnership (OCP-IP).

About Avertec
Avertec SA is a privately held company created in 1998. It is headquartered in the Paris area, France, has a sales office in San Jose, California and represented by distributors in Asia. Its mission is to provide solutions for the back-end verification of complex designs. The company develops and commercializes solutions for Timing, Crosstalk, Power and IR Drop analysis. Avertec has an innovative Transistor level methodology based on proven HiTAS and YAGLE platforms. Realistic full chip validation is provided by combining Static and Dynamic analysis of an abstracted Timing and/or Functional model that is close to the physical implementation.

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