Aldec gives SoC Software Engineers early access to Hardware Aldec Inc. presents on Platform Validation at Verification Futures 2012

Henderson, NV – November 5, 2012 –  Aldec, Inc. is presenting a paper on Platform Validation at Verification Futures 2012 in Windsor, United Kingdom, on Monday 19th November; where Platform Validation is at the heart of SoC hardware and software co-verification, and currently one of the EDA industry’s hottest topics.

With technology trends, such as embedded processors, and time-to-market pressures, concurrent engineering demands that software engineers have early access to silicon. Platform Validation extends beyond the realms of hardware design simulation and functional verification (for which Aldec is perhaps best known) and pushes into system hardware and software co-verification.

Jacek Majkowski, Senior Hardware Engineer with Aldec will be presenting the Platform Validation paper and comments: “Whilst embedded system complexity is growing very fast, driven by high customer expectations, verification tools need to keep pace by providing hardware-based methodologies for SoC designers. The complexity grows in both setup of the design under test and the runtime stage of the test. With Aldec’s new HES-7™ platform, setup of the high capacity designs is far simpler with the ability to scale the available capacity of the tool, while Standard Co-Emulation Modeling Interface (SCE-MI) interface provides an efficient and standardized way to test the design on an emulation platform.”

Importantly, Aldec provides simulator and hardware boards with software that automates (design) mapping to FPGAs. In addition, thanks to Universal Verification Methodology (UVM), SCE-MI methodologies and supporting hardware/interfaces, it is possible to move freely between hardware simulation, emulation and system prototyping.

Moreover, Aldec’s HES-7 boards can be used in different configurations at different phases of a project. For example, four boards (with two Xilinx® Virtex®-7 FPGAs each) could be used by four engineers (hardware or software) as desktop prototyping platforms; to work on separate parts of the design. Moving toward system integration, a backplane can be used to connect the four HES-7 boards together; delivering the equivalent of 96 million ASIC gates.

Majkowski’s presentation will cover an overview on transaction-based verification technologies, including SCE-MI macro-based and Direct Programming Interface (DPI) function-based synthesizable transactors, eliminating communication bottlenecks that could compromise the performance of hardware emulation systems. Real-life use cases will be shown, as well as two detailed customer case studies on transaction-based verification of large ASICs.

Now in its second year, Verification Futures is organized and run by test and verification services company TVS and the Electronic Chips & Systems design Initiative (ECSI). Engineers wishing to register to attend Verification Futures 2012 in Windsor on 19th November can do so by clicking  here.  

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.  www.aldec.com


Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.

Media Contact:

Christina Toole, 
Aldec, Inc. 
+1.702.990.4400
Email Contact
www.aldec.com





Review Article Be the first to review this article
CST: Webinar September 14, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
ESD Alliance, San Jose State University to Host Jim Hogan Talk on “IR4: The Cognitive Era” at San Jose State University Student Union Theater 211 South 9th Street San Jose CA - Sep 20, 2017
IEEE Electronic Design Processing Symposium 2017 at 673 S. Milpita Blvd Milpitas CA - Sep 21 - 22, 2017
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise