Altera First to Benchmark Complex High-Performance Floating-Point Digital Signal Processing Designs on 28 nm FPGAs

Altera's DSP Builder Advanced Blockset™ Design Flow Verified by BDTI, the Industry's Most Trusted Source of Independent DSP Technology Analysis

SAN JOSE, Calif., Oct. 29, 2012 — (PRNewswire) — Altera Corporation (NASDAQ: ALTR) today announced it is first in the industry to successfully benchmark complex, high-performance floating-point digital signal processing (DSP) designs on 28 nm FPGA devices. Independent technology analysis firm Berkeley Design Technology, Inc. (BDTI) verified the efficiency and ease-of-use of Altera's floating-point DSP design flow as well as the performance of demanding floating-point DSP applications on Altera's Stratix® V and Arria® V 28 nm FPGA development kits. Read BDTI's complete FPGA floating-point DSP analysis at

Altera's floating-point DSP design flow is architected to quickly accommodate design changes with parameterizable interfaces in an environment that includes MATLAB and Simulink from MathWorks, as well as Altera's DSP Builder Advanced Blockset, enabling FPGA designers to implement and verify complex floating-point algorithms faster than is possible with traditional HDL-based design. The design flow is ideal for designers incorporating high-performance DSP in applications such as radar, wireless base station, industrial automation, instrumentation and medical imaging applications.

"Altera's floating-point solution enables designers to easily use the massive amounts of high-performance floating-point resources available on an FPGA for DSP data paths," said Alex Grbic, director, product marketing at Altera. "By benchmarking our solution with BDTI, Altera debunks the myth that FPGAs are limited to high-performance fixed-point processing."

For this study, BDTI benchmarked matrix equation solvers using Cholesky and QR decomposition. Matrix inversion is representative of the type of processing used in radar systems, multiple-input multiple-output (MIMO) wireless systems, medical imaging and many other DSP applications.

In the evaluation of Altera's floating-point design flow, BDTI stated, "The Altera floating-point design flow simplifies the process of implementing complex floating-point DSP algorithms on an FPGA by streamlining the tools under a single platform." The report adds, "This integration enables quick development and rapid design space exploration both at the algorithmic level and at the FPGA level, and ultimately reduces overall design effort." 

Altera's DSP Builder is available now for download. Additionally, Altera's DSP Development Kit, Stratix V Edition, and Arria V FPGA Development Kit are also available. For more information about Altera's DSP solutions, please visit

About Altera
Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at Follow Altera via Facebook, RSS and Twitter.

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at

© 2012 The MathWorks, Inc. MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See for a list of additional trademarks. Other product or brand names may be trademarks or registered trademarks of their respective holders.

Editor Contacts:
Shannon Giusti
Altera Corporation
(408) 544-7472
Email Contact

SOURCE Altera Corporation

Altera Corporation

Review Article Be the first to review this article

Featured Video
Applications Engineer for intersil at Palm Bay, Florida
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Design Verification Engineer for intersil at Morrisville, North Carolina
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise