Aprisa and Apogee support double patterning-compliant design rules while maintaining desirable routability for complex designs at 20nm
SANTA CLARA, Calif. — (BUSINESS WIRE) — October 10, 2012 — ATopTech, the leader in next generation physical design solutions, today announced that Aprisa™ and ApogeeTM, the company’s place and route solution, are included in TSMC’S 20nm Reference Flow. TSMC’S 20nm process technology delivers better performance and lower power consumption than previous generations. TSMC and ATopTech collaborated in incorporating ATopTech tools in the 20nm Reference Flow to address the increasing design challenges for 20nm.
Many new technologies have been developed in Aprisa and Apogee to enable customer design successes at 20nm:
- Double patterning technology (DPT) routing rule support
- Color-aware routing
- Hierarchical design flow for DPT routing
- Vt-min width compliance
- GDS voltage marker for spacing check
- TCD/ICOVL insertion
- Boundary cell insertion
“ATopTech's P&R technology is architected specifically for advanced technology design,” said Jue-Hsien Chern, CEO of ATopTech. “We have worked closely with TSMC to develop enhancements to ensure the highest possible routability for optimal manufacturing for 20nm designs. The adoption from TSMC’s 20nm Reference Flow continues our mission to provide customers with best in class physical design tools for advanced processes.”
“We are pleased to include ATopTech’s Aprisa P&R tool into the TSMC 20nm Reference Flow,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “The close collaboration between ATopTech and TSMC will help enable successful 20nm projects for our joint customers.”
Aprisa is a complete place-and-route (P&R engine), including placement, clock tree synthesis, optimization, global routing and detailed routing. The core of the technology is its hierarchical database. Built upon the hierarchical database are common “analysis engines”, such as RC extraction, design rule checking (DRC) engine, and an advanced, extremely fast timing engine to solve the complex timing issues associated with OCV, signal integrity (SI) and multi-corner multi-mode (MCMM) analysis. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process. Because of this advanced architecture, Aprisa is able to deliver predictability and consistency throughout the flow, and hence faster total turn-around time (TAT) and best quality of results (QoR) for physical design projects.
Apogee is a full-featured top-level physical implementation tool that includes proto-typing, floor-planning, and chip-assembly. The unified hierarchical database enables a much more stream-lined hierarchical design flow. Unique In-Hierarchy-Optimization (iHO) technology helps to close top-level timing during Chip-Assembly through simultaneous optimization at top-level and at blocks, reducing the turn-around time for top-level timing closure from weeks to days.
ATopTech, Inc. is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com
Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.
Cayenne Communication LLC
Michelle Clancy, 252-940-0981