SPTS Signs Joint Development Program (JDP) for 300mm 3D-IC Application with Fraunhofer IZM ASSID

Fraunhofer ASSID center adds PECVD capability to 300mm device stacking line

NEWPORT, United Kingdom, Oct. 9, 2012 — (PRNewswire) — SEMICON Europa -- SPTS Technologies, a supplier of advanced wafer processing solutions for the global semiconductor industry and related markets, today announced that it has signed a JDP Program with ASSID from Fraunhofer-IZM to research sub-175 degrees C dielectric films in through silicon vias (TSV) for 3D-IC packaging. The program will use 300mm APM plasma enhanced chemical vapor deposition (PECVD) modules installed on a Versalis® platform alongside SPTS etch chambers in the All Silicon System Integration Dresden (ASSID) centre in Dresden, Germany.

ASSID was set up in 2010, to develop 3D integration technologies on 300mm wafers, enabling leading device manufacturers to apply 3D-IC technology in volume production. By integrating the PECVD modules with etch processes on a single wafer handler, ASSID uses the Versalis system to optimize process results and reduce capital expenditure for development and pilot production. 

The APM offers unique low temperature PECVD processes, targeting via-last TSV applications and via-reveal passivation. Dielectric layers for TSV isolation can be deposited at temperatures below 175 degrees C to provide high sidewall coverage, low stress and proven 'in-via' electrical performance. For via-reveal, the APM offers high deposition rate silicon oxide and nitride films, compatible with silicon-on-glass substrates and combining excellent coverage, barrier properties and electrical isolation.

M. Juergen Wolf, the Manager of Fraunhofer IZM-ASSID and head of division HDI&WLP /ASSID said, "SPTS has been a important partner, who contributes valuable experience and production experience for our 300mm 3D device stacking assembly line.  The additional PECVD capability provided another important process step in this line."

Kevin T. Crofton, executive vice president and chief operating office added, "We're delighted to be a part of Fraunhofer's 300mm development line. SPTS is a leader in integrated 3D-IC solutions and we expect the advanced work Fraunhofer-IZM performed on our etch and PECVD process capabilities to accelerate the adoption of 3D packaging by volume manufacturers.

About Delta PECVD Systems
Delta PECVD Systems offer productive, single-wafer processes for the deposition of dielectric films on wafer sizes up to 300mm. The PECVD chamber is supported by all SPTS cluster platforms and also by the unique Versalis fxP hybrid cluster system. A single chamber design supports multiple wafer sizes. Digital control of critical hardware components gives precise and repeatable process performance across a range of applications, with a unique platen design enabling <200 degrees C deposition temperatures. Key Delta applications include; ultra-uniform silicon nitride for GaAs RFIC capacitor, low temperature dielectrics for advanced packaging and tuned-stress films for MEMS.

About SPTS Technologies
SPTS Technologies designs, manufactures, sells, and supports etch, PVD, CVD and thermal capital equipment and process technologies for the global semiconductor industry and related markets. These markets include MEMS, advanced packaging, LEDs, high speed RF on GaAs and power management. Formerly known as SPP Process Technology Systems, the company was acquired by its management in June 2011, backed by European private equity firm Bridgepoint. Prior to the acquisition, SPTS was a wholly-owned subsidiary of Sumitomo Precisions Products Co. Ltd., formed from the merger of Surface Technology Systems (STS) and acquired assets of Aviza Technology in 2009. For more information about SPTS Technologies, please visit www.spts.com

SOURCE SPTS Technologies

SPTS Technologies
Evelyn Tay
Phone: +65-8383-0393
Email Contact
Web: http://www.spts.com

Review Article Be the first to review this article
Featured Video
More Editorial  
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
ASIC Design Engineer for Ambarella at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Verification Engineer for Ambarella at Santa Clara, CA
Technical Support Engineer Germany/UK for EDA Careers at San Jose, CA
Engr, Elec Des 2 for KLA-Tencor at Milpitas, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy