Palo Alto, California -- Oct 5th, 2012 -- IP Cores, Inc., California, USA has announced a new forward error correction core that supports the future IEEE 100 Gbps standard.
“New Reed-Solomon cores extend our portfolio of error-correction encoders and decoders ,” said Dmitri Varsanofiev, CTO of IP Cores, Inc. “These products will speed up the design cycles in the heating up 100 Gbps backplane Ethernet market. Our developers will keep tracking the progress of the fast-moving IEEE 802.3bj standardization group, so that our customers always have access to the FEC IP cores that are reflecting the Clause 91 in the latest draft of the standard”.
IEEE 802.3bj Backplane Ethernet
IEEE 802.3bj standardization group aims to add the 4-lane 100 Gbps PHY to the IEEE 802.3 Ethernet specification for operation on backplanes and twinaxial copper cables to provide a lower cost, lower power, and higher density solution than the current 100GBASE-CR10 standard.
The base FEC cores support the RS(528, 514) Reed-Solomon code that us used in the 100GBASE-CR4 or 100GBASE-KR4 PHYs of the draft standard. An RS(544, 514) option for 100GBASE-KP4 PHY is also available. IP cores are available for an immediate delivery.