Synopsys Insight Newsletter: Featuring FinFET Design Tools Video and Insights from AMD and Xilinx.

Synopsys Insight Banner

Issue 03, 2012
Partner Highlight
Achieving Faster Design Closure with Early RTL Exploration
Learn as experts from AMD and Synopsys discuss how early RTL exploration with Synopsys' DC Explorer can accelerate the development of high-quality RTL and constraints.

Managing Design Density for Improved Manufacturability and Faster Closure at Advanced Nodes
IC designers are familiar with metal fill as a requirement for improving the planarity of wafers and die and enhancing overall lithographic error margin. Synopsys and AMD discuss the challenges of density management and introduce Fill-to-Target (FTT) technology in IC Validator.
Technology Update
FinFET: The Promises and the Challenges
One of the newest and most exciting technologies in the industry today is FinFET, but as new challenges around FinFETs arise, new solutions must follow. Learn how experts from Synopsys are working with foundry partners and design teams alike to accelerate this innovative technology.

Next-Generation Xilinx FPGA Flows: Gaining Success Using Synopsys Tools with Xilinx Vivado Place-and-Route Software
The pairing of Xilinx's new Vivado Design Suite with Synopsys' Synplify FPGA synthesis tools enables designers to achieve more capacity and shorter turnaround times from their Xilinx 7 Series FPGA design flows. In this article, Angela Sutton explains how these two products complement each other and accelerate innovative designs.

The Benefits of Static Timing Analysis-Based Memory Characterization
NanoTime is Synopsys' advanced transistor-level static timing analysis tool for custom design and embedded memories. Learn how a breakthrough memory feature addition to NanoTime enables designers to effectively analyze complex transistor circuits and embedded memories overnight.

Building High-Performance Interfaces for Storage, Camera and Displays Using UniPro and UFS Controller IP
Learn about Synopsys' new IP for storage, camera and display interfaces as Hezi Saar discusses DesignWare UFS and UniPro controllers and what the new IP will offer to design teams.

Virtual Prototyping Goes Mainstream
For engineers developing software, easy to use virtual prototyping tools are crucial to get their designs to market faster with higher-quality solutions. In this article, Nithya Ruff discusses the benefits of Synopsys' Virtualizer to accelerate innovation.  

Building an IP-XACT Design and Verification Environment with DesignWare IP
Learn about the IP-XACT standard, how to build and generate IP-XACT IP, and get the IP-XACT view of your components' configuration.

A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes
When prototyping an ASIC within an FPGA, designers must determine how to handle design RTL source files comprising instantiated DesignWare Library Building Block IP, Microcontrollers and AMBA On-Chip Bus IP. This article describes how to implement DesignWare IP in an FPGA-based prototype using a single set of ASIC RTL to drive FPGA synthesis.
Executive Insights
Video Interview with Frank Lee - An Introduction to FinFET Design Tools
Hear from Frank Lee, Vice President of Engineering for Synopsys' Analog Mixed Signal Business Group, as he talks about how Synopsys can help designers accelerate innovation in advanced design nodes with FinFET.
Synopsys Innovation Update
Latest News on Products, Technologies, Services and Solutions to Help Accelerate Innovation
Learn about some of the recent innovations Synopsys is providing its customers to help accelerate the development of better products sooner and more cost effectively.
Standards Column
Global Standards Development Requires Sound Fundamentals
Learn about the development of global technical standards and how the need for a formal setting is imperative for EDA and IP standards development.
Special Announcement
Connect with Experts at
If you are a SoC engineer or a user of verification IP, is your go-to resource for protocol-based verification. In this article, Neill Mullinger gives a brief overview of Synopsys' new technical community website.
Executive Insights Video

Executive Insights Video Frank Lee - An Introduction to FinFET Design Tools


SNUG Keynote Videos

Aart  de  Geus  Critical  Mass  Video Aart de Geus on Critical Mass, Systemic Complexity and Innovation


Chenming  Hu  3D  FinFET  Video Dr. Chenming Hu on 3D FinFET - New Structure Extends the Life of the Transistor!


John  Cornish  Low  Power  Video John Cornish on Partnering for Low Power


Recent Articles

Get a Head Start: Early Software Bring-up for ARM big.LITTLE Processing

Low Power is Everywhere

Delivering Great Audio with an SoC-Ready IP Subsystem

Past Issues

Sign Up Now
Sign up for Synopsys Insight quarterly e-newsletter
©2012 Synopsys. All rights reserved. | > about | > privacy |

Synopsys, Inc. | 700 East Middlefield Road, Mountain View, CA 94043
650.584.5000 or 800.541.7737

Review Article Be the first to review this article
Cadsoft: CS EAGLE

Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Sorrow: like sands through the hourglass
More Editorial  
Sr. Field Applications Engineer, CA for Real Intent at Sunnyvale, or San Diego, CA
Sr. R&D Engineer for Real Intent at Sunnyvale, CA
DRC EDA Developer for EDA Careers at San Jose, CA
WEB SW Engineer for EDA Careers at San Jose, CA
R&D/Software Engineering US – MA for EDA Careers at Boston Area, MA
Upcoming Events
The Wearable Technology Show USA at Santa Clara Convention Centre, 5001 Great America Pkwy, Santa Clara CA - Dec 1 - 2, 2015
2015 3D ASIP Conference, Dec 15 - 17, 2015 Sofitel San Francisco Bay Hotel, Redwood City, CA at Sofitel San Francisco Bay Hotel 223 Twin Dolphin Dr Redwood City CA - Dec 15 - 17, 2015
The Design & Verification Conference & Exhibition (DVCon 2016) at Doubletree Hotel San Jose CA - Feb 29 - 3, 2016
DATE 2016 - March 14 - 18, 2016, at the International Congress Center Dresden, Germany at International Congress Center Dresden Germany - Mar 14 - 18, 2016
Precision Technologies: One stop solution PCB Fab & Assembly

Internet Business Systems © 2015 Internet Business Systems, Inc.
595 Millich Dr., Suite 210, Campbell, CA 95008
+1 (408) 850-9202 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy