ANSYS and Subsidiary Apache Receive TSMC 20 nm Phase I Certification

PITTSBURGH, June 4, 2012 — (PRNewswire) — ANSYS (NASDAQ: ANSS) and subsidiary Apache Design announced today that their RedHawk™ and Totem™ products achieved TSMC Phase I 20 nm certification. TSMC certified the tools for 20 nm design rule manuals (DRMs) and SPICE models. Early adopters are using the flows and tools while close collaboration continues between TSMC, ANSYS, Apache and designers.

RedHawk and Totem provide power, noise and reliability signoff for system-on-chip and mixed-signal designs at advanced technology nodes. RedHawk also addresses electromigration by delivering current direction-aware, metal topology-aware and temperature-aware checks as well as expanded capabilities to support TSMC's 20 nm electromigration rules. Totem provides full-chip, layout-based power and noise analysis for analog and mixed-signal designs.

In addition, ANSYS technologies interface with TSMC's 3D-IC flow to deliver accurate thermal profiles through iterative analysis of power maps and boundary conditions.

"Apache delivers innovative solutions that address power, noise and reliability challenges for the most advanced process nodes and emerging design technologies," said Andrew Yang, president of Apache, a subsidiary of ANSYS. "Our collaboration with TSMC enables us to provide optimized tools and methodologies for advanced-technology designers."

"With ANSYS and Apache 20 nm certification at TSMC, companies will be able to produce more robust designs and deliver next-generation products to the marketplace," said Suk Lee, TSMC senior director, design infrastructure marketing division.

The ANSYS/Apache portfolio of product offerings will be showcased at DAC exhibit booth #1813.

About Apache Design, Inc.

Apache Design, an ANSYS subsidiary, enables simulation-driven IC and electronic systems design by providing advanced chip-level power analysis, optimization, and sign-off solutions. Apache's integrated products and methodologies advance low-power innovation and address chip-package-system power and noise challenges. Using Apache's engineering simulation software early in the design and throughout the process enables the world's top semiconductor companies to gain a competitive advantage delivering more power-efficient, high-performance, and noise immune chips. Apache's products help lower power consumption, increase operating performance, mitigate design risks, reduce system cost, and shorten time-to-market for a broad range of end-markets and applications. Learn more at:  http://www.apache-da.com/.

About ANSYS, Inc.

ANSYS brings clarity and insight to customers' most complex design challenges through fast, accurate and reliable engineering simulation. Our technology enables organizations ― no matter their industry ― to predict with confidence that their products will thrive in the real world. Customers trust our software to help ensure product integrity and drive business success through innovation. Founded in 1970, ANSYS employs more than 2,200 professionals, many of them expert in engineering fields such as finite element analysis, computational fluid dynamics, electronics and electromagnetics, and design optimization. Headquartered south of Pittsburgh, U.S.A., ANSYS has more than 65 strategic sales locations throughout the world with a network of channel partners in 40+ countries. Visit www.ansys.com for more information.

ANSYS and any and all ANSYS, Inc. brand, product, service and feature names, logos and slogans are registered trademarks or trademarks of ANSYS, Inc. or its subsidiaries in the United States or other countries. All other brand, product, service and feature names or trademarks are the property of their respective owners.

ANSS-G

Contact

Media

Yukari Ohno

408.457.2000

yukari.ohno@ansys.com

Fran Hensler

724.514.2967

fran.hensler@ansys.com


Investors

 

Annette Arribas

724.514.1782

annette.arribas@ansys.com

 

SOURCE ANSYS, Inc.

Contact:
ANSYS, Inc.
DAC
Apache Design
Web: http://www.ansys.com




Review Article Be the first to review this article
Aldec Webinar Nov 30

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Computer History Museum: the Future of War is Here
More Editorial  
Jobs
Senior SW Developer for EDA Careers at San Jose, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise