Sibridge Technologies Announces USB 3.0 Host and Device Design IP

Leading provider of design & verification IPs will showcase IP portfolio integrated with Axiom's high-performance MPSim simulator at DAC 2012t

Santa Clara, California, May 31, 2012: Sibridge Technologies, a leading provider of design and verification IPs as well as System/SoC design and verification services announced the availability of their USB 3.0 host and device design IP. The company had earlier announced the availability of their USB 3.0 verification IP.  The company will showcase the USB 3.0 host and device design IP as well as the verification IPs running on Axiom Design Automation's MPSim high performance SystemVerilog simulator in booth #1625 during the 49th Design Automation Conference (DAC), from June 4-6, at the Moscone Center in San Francisco.

Sibridge's USB 3.0 design IP includes host and device. The USB 3.0 controller IP is a high performance, low gate count, xHCI (Extensible Host Controller Interface)-compliant semiconductor IP designed for USB 3.0 implementations in ASIC and FPGAs. The USB 3.0 IP provides extensive IP configurability, delivers more than 10x the data transfer rate of USB 2.0 and is backwards compatible with earlier USB technologies. The Sibridge IP's low footprint and high performance makes it ideal for computing, networking, mobile and streaming media devices. The silicon-proven IP reduces the risk and design integration time in today's complex SoCs.

"Sibridge's comprehensive portfolio of silicon-proven design IPs, industry-proven verification IPs and System/SoC design services have enabled over 30 leading semiconductor companies accelerate time-to-market on their high-end designs" said Rajesh Shah, CEO, Sibridge Technologies. "With the addition of these latest USB 3.0 IPs, our customers will be able to continue leveraging Sibridge's portfolio of design and verification IPs coupled with design and verification services to meet their aggressive time-to-market needs."

"Our partnership with Sibridge enabled us to tightly integrate and validate Sibridge's best-in-class design and verification IPs with Axiom's production proven high performance SystemVerilog simulator" stated Tarak Parikh, Vice President of Product Engineering at Axiom Design Automation. "Axiom's renowned debugging capability, now extended to include validated verification and design IP, offers customers an unprecedented, completely integrated  design and verification platform for accelerating the creation of testbenches for quick debugging and verification of  the most complex SOCs".

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