EdXact Releases Version 5.3 of Jivaro reduction platform

First industrial solution to reduce active components

May 24, 2012 -- Grenoble, France -- Backend verification specialist EdXact SA today announces the availability of a new version of Jivaro™, version 5.3. The upgrade has been released for its Jivaro-D product. The tool received a host of new features and new abilities. One of the major product innovations includes the reduction of active components.

EdXact's Jivaro reduction platform allows designers to reduce the burden on post-layout simulation time and memory footprint that comes along with the back-annotation of layout parasitics into the netlist. Since 2005 Jivaro has been in industrial usage by major semiconductor companies, out of which selected partners have participated in beta testing the new features.

Until version 5.2, Jivaro was dedicated to the reduction of passive components, such as resistors, capacitors, inductors, and controlled current and voltage sources. Version 5.3 now can reduce the impact of active components, such as transistors.

Typically Jivaro is used for spice-based simulations of post-layout transistor- and gate-level netlists, which need to be carried out with good accuracy and therefore need to incorporate parasitic effects. Users of Jivaro generally use advanced technology nodes reaching from 90nm down to 22nm. Industrial applications are memory blocks, analog IPs, RF blocks, mixed-signal circuits, high-speed interfaces, ADC, image sensors and their interfaces and others. 

On top of the inclusion of new and innovative algorithms, Jivaro™ has been integrated into Alps™, EdXact's Graphical User Environment, and has received a very tight link into Cadence's design framework. This link allows designers to generate extracted views for designs that are generally too big to deal with natively.

About EdXact

Founded in 2004, EdXact SA focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with sales offices in Japan, Korea and Taiwan.

For additional information: http://www.edxact.com

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