Axiom Introduces Revolutionary Licensing Model For The EDA Industry

Offers Unlimited Worldwide Site License for a Fixed Price  

Milpitas, California, May 23, 2012 --Axiom Design Automation, provider of fastest path to verification closure for semiconductor design, today announced the availability of WUL -- Worldwide Unlimited Licensing; to help customers manage the skyrocketing cost of functional verification of complex semiconductor chips.

Due to the growing complexity of today’s semiconductor chip designs, which may include multiple cores, graphics engines, signal processing engines and various complex interfaces, functional verification has become the biggest impediment to successful chip design. The complexity and cost of verifying these designs is growing exponentially, requiring literally thousands of simulation licenses. The (per seat) time based licensing (TBL) model currently prevalent in EDA industry does not accommodate these customer needs and makes timely completion of functional verification either impossible or extremely cost prohibitive.

Recognizing this breakdown of the current licensing model, Axiom pioneered the concept of Worldwide Unlimited Licensing (WUL); enabling users to get unlimited simulation licenses at a fixed cost, usually in the affordable sub-million dollar range for semiconductor companies with revenues under $500M.

“At Axiom, we have always been focused on solving our customers’ verification problems”, said Badru Agrawala, President and CEO, Axiom Design Automation. “With our continuous innovation in multi-CPU simulation, multi-core waveform dumping, coverage closure and the industry’s most advanced UVM debug capabilities, we have been in the forefront of recognizing and solving the most pressing verification challenges. We recognized the broken TBL model early on and introduced the WUL model to a select customer base. The response was overwhelming. We have several customers who have already adopted this model and have successfully taped-out very complex chips in record time with our production proven MPSim simulator. Now we have decided to roll it out and make it available to everyone”.

“Simulation still remains the main workhorse for functional verification”, stated Gary Smith, President of Gary Smith EDA. “Axiom’s move to offer an affordable, fixed price for unlimited simulation licenses is a big step forward in helping curb the escalating cost of verification. This new licensing model makes deploying large verification farms feasible for small to mid size semiconductor companies, enabling them to meet their aggressive verification schedules with manageable cost. This new innovative pricing model could be the catalyst that is needed to encourage new startups and revive the semiconductor industry”.

Axiom’s  MPSim is industry’s price/performance leading SystemVerilog verification platform. MPSim offers significant new capabilities in simulation performance, debugging, coverage analysis and SystemVerilog enhancements including the newly released UVMDesigner and complete support for VMM, OVM and UVM. Combined with multi-core support, compiled testbench including SystemVerilog and OpenVera, comprehensive coverage closure technology and best-in-class integrated graphical debugger, MPSim offers the most complete verification solution in a single unified kernel architecture for maximum performance.

About Axiom

Axiom Design Automation is a company focused on providing the best-in-class verification platform to address the growing complexity of today’s FPGAs, ICs, SOCs and systems. Axiom’s flagship product, MPSim is the state-of-the-art, industry proven high performance SystemVerilog simulator integrated with an advanced debugger, compiled testbench automation, multiple clock domain verification and comprehensive coverage analysis for quick verification closure. MPSim incorporates SystemVerilog and OpenVera testbench automation with SVA and coverage analysis in single kernel architecture for maximum performance. MPSim is fully compliant with industry standards such as VMM, OVM, UVM, UPF, etc. For more information please visit www . axiom - da . com.

For more information, contact:
Ghulam Nurie
Email Contact

 





Review Article Be the first to review this article
CST: Webinar September 14, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
FPGA Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise