MEDIA ALERT: Verific Exhibits at 49th Design Automation Conference and Hosts DAC Tuesday Night Reception

ALAMEDA, CA -- (Marketwire) -- May 23, 2012 -- AT DAC BOOTH #1807

WHO: Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog and VHDL parsers and elaborators

WHAT:
Will exhibit at the 49th Design Automation Conference in booth #1807 and host the DAC Tuesday Night Reception

WHEN:
Exhibits will be open Monday-Wednesday, June 4-6, from 9 a.m.-6 p.m. The Tuesday Night Reception will be held from 6-7 p.m.

WHERE:
Moscone Center, South Hall, San Francisco. The Tuesday Night Reception will be held in Room 303/Outside Terrace.

WHY:
Verific's DAC theme, "Build Your Own Register Transfer Level (RTL) Tools," invites computer-aided design (CAD) managers and system-on-chip (SoC) designers to find out how they can build their own internal RTL-based electronic design automation (EDA) tools with Verific's Perl application program interface (API).

Verific's software is also to be found in 32 other DAC exhibitor booths, serving as the front end to EDA and FPGA analysis, simulation, verification, synthesis, emulation and test tools. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF.

For more details about Verific, visit www.verific.com.

Information on DAC can be found at www.dac.com.

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins 
Public Relations for Verific 
(617) 437-1822

Email Contact  





Review Article Be the first to review this article

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise