OCP-IP Releases OCP 3.1 Specification into Member Review

BEAVERTON, Ore. — (BUSINESS WIRE) — May 23, 2012 — Open Core Protocol International Partnership (OCP-IP) has released the OCP 3.1 specification into member review. OCP 3.1 adds several important capabilities, including: Flexible memory barriers, transaction counting parameters, transitions from proprietary OCP RTL.Conf files to the Accellera IP-XACT metadata format, and new cache coherence compliance material. These new features allow engineers to leverage OCP to ensure IP reuse on the world’s most advanced leading-edge designs regardless of on chip architecture or which processor cores are featured.

In high performance systems featuring multiple processors, deep pipelining of memory transactions is needed to cover the high latency of external DRAM that exposes the system to complex ordering challenges where one core may see memory as inconsistent with respect to the operations of another core. By introducing memory barriers, OCP interfaces take advantage of performance-enhancing features such as write posting while using barrier commands to enforce system ordering so that other cores will see the effects of critical memory updates in the expected order.

OCP supports deep transaction pipelining across several request and response phases. As such it is valuable to understand the number of outstanding transactions that each side of the interface can manage. The new transaction counting parameter extension in OCP 3.1 facilitates automated transaction buffer sizing, protocol checking and formal verification of OCP interfaces based on the maximum transaction count supported for each OCP tag, thread and interface.

The latest version of the specification now utilizes the industry-standard IP-XACT format as the preferred metadata format, based on a set of approved extensions proposed by the OCP-IP Metadata Working Group and deprecates the original OCP-proprietary formats. This enables ready integration of OCP-based cores into IP-XACT compliant design environments.

Lastly, for convenience, OCP 3.1 has been re-structured separating the base Specification from the new Compliance chapters. Additionally, the OCP-IP Functional Verification Working Group provided protocol compliance, configuration compliance and functional coverage point details for the cache coherence extensions that were originally introduced in OCP 3.0. This substantial addition greatly streamlines the process of verifying cache-coherent systems, which is one of the most challenging areas of functional verification.

For all the latest information on OCP-IP, please see our latest newsletter at: http://www.ocpip.org/newsletters.php.

About OCP-IP

Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.

NOTE: All trademarks and service marks are the property of their respective owners.



Contact:

OCP-IP
Ian Mackintosh, 408-761-5980
Email Contact
or
Joe Basques, 512-551-3377
Email Contact




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Blue Pearl: Best kept Secret in EDA
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise