Call for Papers ASP-DAC 2013
| | Rate | Review | Notices

 

18th Asia and South Pacific Design Automation Conference 2013

        Jan. 22-25, 2013, Pacifico Yokohama, Yokohama, Japan

Aims of the Conference:

ASP-DAC 2013 is the eighteenth annual international conference on VLSI design automation in Asia and South Pacific region, one of the most active regions of design and fabrication of silicon chips in the world.

The conference aims at providing the Asian and South Pacific CAD/DA and Design community with opportunities of presenting recent advances and with forums for future directions in technologies related to Electronic Design Automation (EDA). The format of the meeting intends to cultivate and promote an instructive and productive interchange of ideas among EDA researchers/developers and system/circuit/device designers. All scientists, engineers, and students who are interested in theoretical and practical aspects of VLSI design and design automation are welcomed to ASP-DAC.

Areas of Interest:

Original papers on, but not limited to, the following areas are invited.

Please note that ASP-DAC will work cooperatively with other conferences and symposia in the field to check for double submissions.

[1] System-Level Modeling and Simulation/Verification:

System-level modeling, specification, language, performance analysis, system-level simulation/verification, hardware-software co-simulation/co-verification, etc.

[2] System-Level Synthesis and Optimization:

System-on-chip and multi-processor SoC (MPSoC) design methodology, hardware-software partitioning, hardware-software co-design, IP/platform-based design, application-specific instruction-set processor

(ASIP) synthesis, low power system design, etc.

[3] System-Level Memory/Communication Design and Networks on Chip:

Communication-based architecture design, network-on-chip (NoC) design methodologies and CAD, interface synthesis, system communication architecture, memory architecture, low power communication design, etc.

[4] Embedded and Real-Time Systems:

Embedded system design, real-time system design, OS, middleware, compilation techniques, memory/cache optimization, interfacing and software issues.

[5] High-Level/Behavioral/Logic Synthesis and Optimization:

High-Level/behavioral/RTL synthesis, technology-independent optimization, technology mapping, interaction between logic design and layout, sequential and asynchronous logic synthesis, resource scheduling, allocation, and synthesis.

[6] Validation and Verification for Behavioral/Logic Design:

Logic simulation, symbolic simulation, formal verification, equivalence checking, transaction-level/RTL and gate-level modeling and validation, assertion-based verification, coverage-analysis, constrained-random testbench generation.

[7] Physical Design:

Floorplanning, partitioning, placement, buffer insertion, routing, interconnect planning, clock network synthesis, post-placement optimization, layout verification, package/PCB routing, etc.

[8] Timing, Power, Thermal Analysis and Optimization:

Deterministic and statistical static timing analysis, statistical performance analysis and optimization, low power design, power and leakage analysis, power/ground and package analysis and optimization, thermal analysis, etc.

[9] Signal/Power Integrity, Interconnect/Device/Circuit Modeling and Simulation Signal/power integrity, clock and bus analysis, interconnect and substrate modeling/extraction, package modeling, device modeling/simulation, circuit simulation, high-frequency and electromagnetic simulation of circuits, etc.

[10] Design for Manufacturability/Yield and Statistical Design:

DFM, DFY, CAD support for OPC and RET, variability analysis, yield analysis and optimization, reliability analysis, design for resilience and robustness, cell library design, design fabrics, etc.

[11] Test and Design for Testability:

Testable design, fault modeling, ATPG, BIST and DFT, memory test and repair, core and system test, delay test, analog and mixed signal test.

[12] Analog, RF and Mixed Signal Design and CAD:

Analog/RF synthesis, analog layout, verification and simulation techniques, noise analysis, mixed-signal design considerations.

[13] Emerging Technologies and Applications i. Design case studies for emerging applications: multimedia, consumer electronics, communication, networking, ubiquitous computing and biomedical applications, etc. ii. Post CMOS technologies: nanotechnology, quantum, optical interconnect, 3D integration, probabilistic architecture, emerging memory technologies, microfluidics, molecular, bioelectronics, etc., with emphasis on modeling, analysis, novel circuit/architecture, CAD tools, and design methodologies.

* ASP-DAC 2013 University LSI Design Contest encourages submitting original papers on LSI design and implementation at universities and other educational organizations.

- Submission of Papers:

  Deadline for submission:    5 PM JST (UTC+9) July 13 (Fri.), 2012

  Notification of acceptance:                  Sep. 12 (Wed.), 2012

  Deadline for final version: 5 PM JST (UTC+9) Nov. 14 (Wed.), 2012

  Specification of the paper submission format is available at the WEB site:

  http://www.aspdac.com/aspdac2013/

Prospective Sponsors:

  ACM SIGDA, IEEE CASS, IEICE ESS, IPSJ SIG-SLDM

ASP-DAC2013 Chairs:

  General Chair:                 Shinji Kimura (Waseda Univ.)

  Technical Program Chair:       Yuan Xie (Pennsylvania State Univ.)

  Technical Program Vice Chairs: Nagisa Ishiura (Kwansei Univ.)

                                 Huazhong Yang (Tsinghua Univ.)

Contact:

  Conference Secretariat: aspdac2013-sec [at] mls.aspdac.com

  TPC Secretariat:        aspdac2013-tpc [at] mls.aspdac.com

 




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy