ALAMEDA, CALIF. – May 9, 2012 – Excellicon, a first-time exhibitor of end-to-end Timing Constraints Solution at the Design Automation Conference (DAC), today announced it adopted Verific Design Automation's industry-standard, IEEE-compliant front-end platform for use with its software for timing constraints authoring, verification and management.
Verific's SystemVerilog and VHDL parsers and register transfer level (RTL) elaborator have been tightly integrated with Excellicon's Timing Constraints Compiler. Excellicon's products are targeted at solving complexity associated with latest requirements in timing constraints, including multi-mode constraints generation, verification and management, as well as full mode analysis capabilities. They will be demonstrated during DAC in Booth #610 June 4-6 at the Moscone Center in San Francisco.
"Selecting Verific's front-end software enabled us to focus on our core competency and get our products to market much faster" remarks Peter Petrov, founder and chief executive officer of Excellicon. "Its reputation for quality, reliable software and excellent support is well earned. The Verific team should be commended for its customer support and service."
Excellicon's Constraints Manager ConMan is based on patented formal technology targeted at solving complex problems facing chip designers, from initial planning through final timing closure where implementation expertise is needed. Its tools provide the infrastructure to develop, track, optimize and verify information for the entire design for faster time to tapeout. They also enable designers to seamlessly propagate constraints for any mode in the design to any layer of hierarchy with ease.
Michiel Ligthart, Verific's president and chief operating officer, says: "We take great pride in working with EDA startups such as Excellicon. It is addressing a critical area of the design flow by tackling timing constraints closure with a promising approach and wisely elected to outsource its front-end software needs to us."
Since its founding in 1999, Verific's software has served as the front end to a wide range of EDA and FPGA tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.
Verific will offer demonstrations of its RTL front-end solutions in DAC Booth #1807. Additionally, its software will be demonstrated in 20 other DAC exhibitor booths.
Founded in 2008, Excellicon is a privately funded EDA company focused on developing software solutions to address timing constraints authoring, verification and management. It offers a unique and new approach to compile and generate constraints correct by construction. Excellicon's patented software is designed for semiconductor professionals from a developer's perspective and covers the spectrum of constraints development, including timing constraints compilation, verification, formal validation and management through a multi-mode approach. It is headquartered in Laguna Hills, Calif. For more information on Excellicon, visit: www.excellicon.com.
About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end solutions supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.