The Cadence Encounter RTL-to-GDSII flow -- including RTL Compiler, the Encounter Digital Implementation System, and Encounter Test -- helps design teams optimize power, performance, and area for the world's most advanced high-performance, low-power SoC designs.
Netronome's OEM customers have tremendous constraints on power budgets, which required the company to optimize its high-performance 40Gbps NFPs for low-power consumption for use in their customers' switches, routers, load balancers and cyber-security platforms. Netronome engineers were tasked with improving chip power efficiencies across multi-mode, multi-corner and on-chip variation scenarios. Implementing robust clock trees that consume less dynamic switching and static leakage power without compromising on performance was difficult under such extreme requirements. Furthermore, as chip power consumption increases, it costs more to design, fabricate, operate and cool devices and systems.
"Using the complete Cadence Encounter RTL-to-GDSII flow, we were able to tape out a complex 1.4 GHz 40-core micro-engine-based Network Flow Processor on schedule, achieving a 29 percent power savings and 10 percent improvement in timing," said Jim Finnegan, senior vice president, Silicon Engineering at Netronome. "We were particularly impressed with the newly integrated Clock Concurrent Optimization ( CCOpt) technology in the Encounter flow and its unique ability to optimize clocks and data-path simultaneously allowing us to eliminate several manual design steps and achieve superior performance, power and area results on our design. This gives us a competitive advantage in our end market."
Clocks are the backbone of all digital chips, and a fundamentally different approach to clock construction and optimization was needed. Traditional clock tree synthesis (CTS) tools and methodologies -- which are based on minimizing skew and are isolated from logic/physical optimization -- are insufficient for advanced node, high-performance designs due to the growing gap between pre- and post-CTS design timing. CCOpt technology bridges the gap by re-focusing CTS directly on timing -- not skew minimization -- and combining this timing-driven CTS with concurrent logic/physical optimization.
"Network Flow processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. It is conditions like these where the Encounter RTL-to-GDSII flow really shines," said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "We applaud Netronome's success and are pleased to see another customer experiencing first-hand the outstanding power, performance, area and time-to-market advantages in Encounter and our breakthrough CCOpt technology."
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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For more information, please contact: Dean Solov Cadence Design Systems, Inc. 408-944-7226 Email Contact